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Commit e8ef868b authored by Markos Chandras's avatar Markos Chandras Committed by Ralf Baechle
Browse files

MIPS: uasm: Add sltu uasm instruction 



It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/6731/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 390363ed

arch/mips/include/asm/uasm.h

+1 −0
Original line number Diff line number Diff line
@@ -144,6 +144,7 @@ Ip_u2s3u1(_sd); 
Ip_u2u1u3(_sll);

Ip_u3u2u1(_sllv);

Ip_u2u1s3(_sltiu);

Ip_u3u1u2(_sltu);

Ip_u2u1u3(_sra);

Ip_u2u1u3(_srl);

Ip_u3u2u1(_srlv);

arch/mips/include/uapi/asm/inst.h

+1 −0
Original line number Diff line number Diff line
@@ -261,6 +261,7 @@ enum mm_32a_minor_op { 
	mm_and_op = 0x250,

	mm_or32_op = 0x290,

	mm_xor32_op = 0x310,

	mm_sltu_op = 0x390,

};



/*

arch/mips/mm/uasm-micromips.c

+1 −0
Original line number Diff line number Diff line
@@ -99,6 +99,7 @@ static struct insn insn_table_MM[] = { 
	{ insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },

	{ insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },

	{ insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },

	{ insn_sltu, M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD },

	{ insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },

	{ insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD },

	{ insn_srlv, M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD },

arch/mips/mm/uasm-mips.c

+1 −0
Original line number Diff line number Diff line
@@ -107,6 +107,7 @@ static struct insn insn_table[] = { 
	{ insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },

	{ insn_sllv,  M(spec_op, 0, 0, 0, 0, sllv_op),  RS | RT | RD },

	{ insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },

	{ insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD },

	{ insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },

	{ insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },

	{ insn_srlv,  M(spec_op, 0, 0, 0, 0, srlv_op),  RS | RT | RD },

arch/mips/mm/uasm.c

+2 −1
Original line number Diff line number Diff line
@@ -53,7 +53,7 @@ enum opcode { 
	insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,

	insn_mfhi, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe,

	insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_sltiu,

	insn_sra, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,

	insn_sltu, insn_sra, insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync,

	insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait,

	insn_xor, insn_xori, insn_yield,

};
@@ -285,6 +285,7 @@ I_u2s3u1(_sd) 
I_u2u1u3(_sll)

I_u3u2u1(_sllv)

I_u2u1s3(_sltiu)

I_u3u1u2(_sltu)

I_u2u1u3(_sra)

I_u2u1u3(_srl)

I_u3u2u1(_srlv)