Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e881dbd5 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
Browse files

iommu/amd: Add support for higher 64-bit IOMMU Control Register 



Currently, the driver only supports lower 32-bit of IOMMU Control register.
However, newer AMD IOMMU specification has extended this register
to 64-bit. Therefore, replace the accessing API with the 64-bit version.

Cc: Joerg Roedel <jroedel@suse.de>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 818b7587

drivers/iommu/amd_iommu_init.c

+13 −13
Original line number Diff line number Diff line
@@ -280,9 +280,9 @@ static void clear_translation_pre_enabled(struct amd_iommu *iommu) 


static void init_translation_status(struct amd_iommu *iommu)

{

	u32 ctrl;

	u64 ctrl;



	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);

	ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

	if (ctrl & (1<<CONTROL_IOMMU_EN))

		iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;

}
@@ -386,30 +386,30 @@ static void iommu_set_device_table(struct amd_iommu *iommu) 
/* Generic functions to enable/disable certain features of the IOMMU. */

static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)

{

	u32 ctrl;

	u64 ctrl;



	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);

	ctrl |= (1 << bit);

	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

	ctrl = readq(iommu->mmio_base +  MMIO_CONTROL_OFFSET);

	ctrl |= (1ULL << bit);

	writeq(ctrl, iommu->mmio_base +  MMIO_CONTROL_OFFSET);

}



static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)

{

	u32 ctrl;

	u64 ctrl;



	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);

	ctrl &= ~(1 << bit);

	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

	ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

	ctrl &= ~(1ULL << bit);

	writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

}



static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)

{

	u32 ctrl;

	u64 ctrl;



	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);

	ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);

	ctrl &= ~CTRL_INV_TO_MASK;

	ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;

	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

	writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);

}



/* Function to enable the hardware */