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Commit e7eda91f authored by Barry Song's avatar Barry Song
Browse files

ARM: prima2: move to generic reset controller driver framework 



this moves to generic IP module reset framework, and make other drivers
use common device_reset() API.

Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
Signed-off-by: default avatarBin Shi <Bin.Shi@csr.com>
Acked-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
parent 951ec090

Documentation/devicetree/bindings/reset/sirf,rstc.txt

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CSR SiRFSoC Reset Controller

======================================



Please also refer to reset.txt in this directory for common reset

controller binding usage.



Required properties:

- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"

- reg: should be register base and length as documented in the

  datasheet

- #reset-cells: 1, see below



example:



rstc: reset-controller@88010000 {

	compatible = "sirf,prima2-rstc";

	reg = <0x88010000 0x1000>;

	#reset-cells = <1>;

};



Specifying reset lines connected to IP modules

==============================================



The reset controller(rstc) manages various reset sources. This module provides

reset signals for most blocks in system. Those device nodes should specify the

reset line on the rstc in their resets property, containing a phandle to the

rstc device node and a RESET_INDEX specifying which module to reset, as described

in reset.txt.



For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.

For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose

rest_bit is in SW_RST1, its RESET_INDEX is 32~63.



example:



vpp@90020000 {

	compatible = "sirf,prima2-vpp";

	reg = <0x90020000 0x10000>;

	interrupts = <31>;

	clocks = <&clks 35>;

	resets = <&rstc 6>;

};

arch/arm/boot/dts/atlas6.dtsi

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@@ -65,9 +65,10 @@ 
				#clock-cells = <1>;

			};



			reset-controller@88010000 {

			rstc: reset-controller@88010000 {

				compatible = "sirf,prima2-rstc";

				reg = <0x88010000 0x1000>;

				#reset-cells = <1>;

			};



			rsc-controller@88020000 {

arch/arm/boot/dts/marco.dtsi

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@@ -58,9 +58,10 @@ 
			#size-cells = <1>;

			ranges = <0xc2000000 0xc2000000 0x1000000>;



			reset-controller@c2000000 {

			rstc: reset-controller@c2000000 {

				compatible = "sirf,marco-rstc";

				reg = <0xc2000000 0x10000>;

				#reset-cells = <1>;

			};

		};

arch/arm/boot/dts/prima2.dtsi

+2 −1
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@@ -76,9 +76,10 @@ 
				#clock-cells = <1>;

			};



			reset-controller@88010000 {

			rstc: reset-controller@88010000 {

				compatible = "sirf,prima2-rstc";

				reg = <0x88010000 0x1000>;

				#reset-cells = <1>;

			};



			rsc-controller@88020000 {

arch/arm/mach-prima2/Kconfig

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config ARCH_SIRF

	bool "CSR SiRF" if ARCH_MULTI_V7

	select ARCH_HAS_RESET_CONTROLLER

	select ARCH_REQUIRE_GPIOLIB

	select GENERIC_CLOCKEVENTS

	select GENERIC_IRQ_CHIP