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Commit e7c587da authored by Borislav Petkov's avatar Borislav Petkov Committed by Thomas Gleixner
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x86/speculation: Use synthetic bits for IBRS/IBPB/STIBP 



Intel and AMD have different CPUID bits hence for those use synthetic bits
which get set on the respective vendor's in init_speculation_control(). So
that debacles like what the commit message of

  c65732e4 ("x86/cpu: Restore CPUID_8000_0008_EBX reload")

talks about don't happen anymore.

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Tested-by: default avatarJörg Otte <jrg.otte@gmail.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>
Link: https://lkml.kernel.org/r/20180504161815.GG9257@pd.tnic
parent 15e6c22f

arch/x86/include/asm/cpufeatures.h

+6 −4
Original line number Diff line number Diff line
@@ -198,7 +198,6 @@ 
#define X86_FEATURE_CAT_L2		( 7*32+ 5) /* Cache Allocation Technology L2 */

#define X86_FEATURE_CDP_L3		( 7*32+ 6) /* Code and Data Prioritization L3 */

#define X86_FEATURE_INVPCID_SINGLE	( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */



#define X86_FEATURE_HW_PSTATE		( 7*32+ 8) /* AMD HW-PState */

#define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */

#define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */
@@ -216,6 +215,9 @@ 
#define X86_FEATURE_USE_IBRS_FW		( 7*32+22) /* "" Use IBRS during runtime firmware calls */

#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE	( 7*32+23) /* "" Disable Speculative Store Bypass. */

#define X86_FEATURE_AMD_SSBD		( 7*32+24)  /* "" AMD SSBD implementation */

#define X86_FEATURE_IBRS		( 7*32+25) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_IBPB		( 7*32+26) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_STIBP		( 7*32+27) /* Single Thread Indirect Branch Predictors */



/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */
@@ -276,9 +278,9 @@ 
#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

#define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */

#define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */

#define X86_FEATURE_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_IBRS		(13*32+14) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors */

#define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */

#define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */

#define X86_FEATURE_AMD_STIBP		(13*32+15) /* "" Single Thread Indirect Branch Predictors */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */

#define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */

arch/x86/kernel/cpu/common.c

+10 −4
Original line number Diff line number Diff line
@@ -757,17 +757,23 @@ static void init_speculation_control(struct cpuinfo_x86 *c) 
	 * and they also have a different bit for STIBP support. Also,

	 * a hypervisor might have set the individual AMD bits even on

	 * Intel CPUs, for finer-grained selection of what's available.

	 *

	 * We use the AMD bits in 0x8000_0008 EBX as the generic hardware

	 * features, which are visible in /proc/cpuinfo and used by the

	 * kernel. So set those accordingly from the Intel bits.

	 */

	if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {

		set_cpu_cap(c, X86_FEATURE_IBRS);

		set_cpu_cap(c, X86_FEATURE_IBPB);

	}



	if (cpu_has(c, X86_FEATURE_INTEL_STIBP))

		set_cpu_cap(c, X86_FEATURE_STIBP);



	if (cpu_has(c, X86_FEATURE_AMD_IBRS))

		set_cpu_cap(c, X86_FEATURE_IBRS);



	if (cpu_has(c, X86_FEATURE_AMD_IBPB))

		set_cpu_cap(c, X86_FEATURE_IBPB);



	if (cpu_has(c, X86_FEATURE_AMD_STIBP))

		set_cpu_cap(c, X86_FEATURE_STIBP);

}



void get_cpu_cap(struct cpuinfo_x86 *c)

arch/x86/kvm/cpuid.c

+5 −5
Original line number Diff line number Diff line
@@ -379,7 +379,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, 


	/* cpuid 0x80000008.ebx */

	const u32 kvm_cpuid_8000_0008_ebx_x86_features =

		F(IBPB) | F(IBRS);

		F(AMD_IBPB) | F(AMD_IBRS);



	/* cpuid 0xC0000001.edx */

	const u32 kvm_cpuid_C000_0001_edx_x86_features =
@@ -648,10 +648,10 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function, 
		entry->eax = g_phys_as | (virt_as << 8);

		entry->edx = 0;

		/* IBRS and IBPB aren't necessarily present in hardware cpuid */

		if (boot_cpu_has(X86_FEATURE_IBPB))

			entry->ebx |= F(IBPB);

		if (boot_cpu_has(X86_FEATURE_IBRS))

			entry->ebx |= F(IBRS);

		if (boot_cpu_has(X86_FEATURE_AMD_IBPB))

			entry->ebx |= F(AMD_IBPB);

		if (boot_cpu_has(X86_FEATURE_AMD_IBRS))

			entry->ebx |= F(AMD_IBRS);

		entry->ebx &= kvm_cpuid_8000_0008_ebx_x86_features;

		cpuid_mask(&entry->ebx, CPUID_8000_0008_EBX);

		break;

arch/x86/kvm/svm.c

+3 −3
Original line number Diff line number Diff line
@@ -4108,7 +4108,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		break;

	case MSR_IA32_SPEC_CTRL:

		if (!msr_info->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_IBRS))

		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))

			return 1;



		msr_info->data = svm->spec_ctrl;
@@ -4203,7 +4203,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 
		break;

	case MSR_IA32_SPEC_CTRL:

		if (!msr->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_IBRS))

		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS))

			return 1;



		/* The STIBP bit doesn't fault even if it's not advertised */
@@ -4230,7 +4230,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 
		break;

	case MSR_IA32_PRED_CMD:

		if (!msr->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_IBPB))

		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))

			return 1;



		if (data & ~PRED_CMD_IBPB)

arch/x86/kvm/vmx.c

+2 −7
Original line number Diff line number Diff line
@@ -3523,9 +3523,7 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		return kvm_get_msr_common(vcpu, msr_info);

	case MSR_IA32_SPEC_CTRL:

		if (!msr_info->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_SSBD))

		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))

			return 1;



		msr_info->data = to_vmx(vcpu)->spec_ctrl;
@@ -3643,9 +3641,7 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		break;

	case MSR_IA32_SPEC_CTRL:

		if (!msr_info->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_IBRS) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_SSBD))

		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))

			return 1;



		/* The STIBP bit doesn't fault even if it's not advertised */
@@ -3675,7 +3671,6 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		break;

	case MSR_IA32_PRED_CMD:

		if (!msr_info->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_IBPB) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))

			return 1;