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Commit e77d99d4 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

Merge tag 'kvm-arm-for-3.18' of... 

Merge tag 'kvm-arm-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-next

Changes for KVM for arm/arm64 for 3.18

This includes a bunch of changes:
 - Support read-only memory slots on arm/arm64
 - Various changes to fix Sparse warnings
 - Correctly detect write vs. read Stage-2 faults
 - Various VGIC cleanups and fixes
 - Dynamic VGIC data strcuture sizing
 - Fix SGI set_clear_pend offset bug
 - Fix VTTBR_BADDR Mask
 - Correctly report the FSC on Stage-2 faults

Conflicts:
	virt/kvm/eventfd.c
	[duplicate, different patch where the kvm-arm version broke x86.
	 The kvm tree instead has the right one]
parents bb0ca6ac 0496daa5

Documentation/virtual/kvm/devices/arm-vgic.txt

+10 −0
Original line number Original line Diff line number Diff line
@@ -71,3 +71,13 @@ Groups: 
  Errors:

  Errors:

    -ENODEV: Getting or setting this register is not yet supported

    -ENODEV: Getting or setting this register is not yet supported

    -EBUSY: One or more VCPUs are running

    -EBUSY: One or more VCPUs are running



  KVM_DEV_ARM_VGIC_GRP_NR_IRQS

  Attributes:

    A value describing the number of interrupts (SGI, PPI and SPI) for

    this GIC instance, ranging from 64 to 1024, in increments of 32.



  Errors:

    -EINVAL: Value set is out of the expected range

    -EBUSY: Value has already be set, or GIC has already been initialized

            with default values.

arch/arm/include/asm/kvm_emulate.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -148,6 +148,11 @@ static inline bool kvm_vcpu_trap_is_iabt(struct kvm_vcpu *vcpu) 
}

}





static inline u8 kvm_vcpu_trap_get_fault(struct kvm_vcpu *vcpu)

static inline u8 kvm_vcpu_trap_get_fault(struct kvm_vcpu *vcpu)

{

	return kvm_vcpu_get_hsr(vcpu) & HSR_FSC;

}



static inline u8 kvm_vcpu_trap_get_fault_type(struct kvm_vcpu *vcpu)

{

{

	return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE;

	return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE;

}

}

arch/arm/include/asm/kvm_host.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -43,7 +43,7 @@ 
#include <kvm/arm_vgic.h>

#include <kvm/arm_vgic.h>





u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);

u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode);

int kvm_target_cpu(void);

int __attribute_const__ kvm_target_cpu(void);

int kvm_reset_vcpu(struct kvm_vcpu *vcpu);

int kvm_reset_vcpu(struct kvm_vcpu *vcpu);

void kvm_reset_coprocs(struct kvm_vcpu *vcpu);

void kvm_reset_coprocs(struct kvm_vcpu *vcpu);

arch/arm/include/asm/kvm_mmu.h

+0 −11
Original line number Original line Diff line number Diff line
@@ -78,17 +78,6 @@ static inline void kvm_set_pte(pte_t *pte, pte_t new_pte) 
	flush_pmd_entry(pte);

	flush_pmd_entry(pte);

}

}





static inline bool kvm_is_write_fault(unsigned long hsr)

{

	unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;

	if (hsr_ec == HSR_EC_IABT)

		return false;

	else if ((hsr & HSR_ISV) && !(hsr & HSR_WNR))

		return false;

	else

		return true;

}



static inline void kvm_clean_pgd(pgd_t *pgd)

static inline void kvm_clean_pgd(pgd_t *pgd)

{

{

	clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));

	clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));

arch/arm/include/uapi/asm/kvm.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -25,6 +25,7 @@ 




#define __KVM_HAVE_GUEST_DEBUG

#define __KVM_HAVE_GUEST_DEBUG

#define __KVM_HAVE_IRQ_LINE

#define __KVM_HAVE_IRQ_LINE

#define __KVM_HAVE_READONLY_MEM





#define KVM_REG_SIZE(id)						\

#define KVM_REG_SIZE(id)						\

	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))

	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
@@ -173,6 +174,7 @@ struct kvm_arch_memory_slot { 
#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)

#define   KVM_DEV_ARM_VGIC_CPUID_MASK	(0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)

#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0

#define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT	0

#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)

#define   KVM_DEV_ARM_VGIC_OFFSET_MASK	(0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)

#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS	3





/* KVM_IRQ_LINE irq field index values */

/* KVM_IRQ_LINE irq field index values */

#define KVM_ARM_IRQ_TYPE_SHIFT		24

#define KVM_ARM_IRQ_TYPE_SHIFT		24