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Commit e7594072 authored by Senthil Balasubramanian's avatar Senthil Balasubramanian Committed by John W. Linville
Browse files

ath9k: Adding support for Atheros AR9285 chipset. 



Signed-off-by: default avatarSenthil Balasubramanian <senthilkumar@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent e8fbc99e

drivers/net/wireless/ath9k/ath9k.h

+1 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#define AR9160_DEVID_PCI	0x0027

#define AR9280_DEVID_PCI	0x0029

#define AR9280_DEVID_PCIE	0x002a

#define AR9285_DEVID_PCIE	0x002b



#define AR5416_AR9100_DEVID	0x000b

drivers/net/wireless/ath9k/calib.c

+98 −0
Original line number Diff line number Diff line
@@ -818,6 +818,101 @@ bool ath9k_hw_calibrate(struct ath_hal *ah, struct ath9k_channel *chan, 
	return true;

}



static inline void ath9k_hw_9285_pa_cal(struct ath_hal *ah)

{



	u32 regVal;

	int i, offset, offs_6_1, offs_0;

	u32 ccomp_org, reg_field;

	u32 regList[][2] = {

		{ 0x786c, 0 },

		{ 0x7854, 0 },

		{ 0x7820, 0 },

		{ 0x7824, 0 },

		{ 0x7868, 0 },

		{ 0x783c, 0 },

		{ 0x7838, 0 },

	};



	if (AR_SREV_9285_11(ah)) {

		REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));

		udelay(10);

	}



	for (i = 0; i < ARRAY_SIZE(regList); i++)

		regList[i][1] = REG_READ(ah, regList[i][0]);



	regVal = REG_READ(ah, 0x7834);

	regVal &= (~(0x1));

	REG_WRITE(ah, 0x7834, regVal);

	regVal = REG_READ(ah, 0x9808);

	regVal |= (0x1 << 27);

	REG_WRITE(ah, 0x9808, regVal);



	REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);

	REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);

	REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);

	REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 1);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);

	ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 7);



	REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);

	udelay(30);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);



	for (i = 6; i > 0; i--) {

		regVal = REG_READ(ah, 0x7834);

		regVal |= (1 << (19 + i));

		REG_WRITE(ah, 0x7834, regVal);

		udelay(1);

		regVal = REG_READ(ah, 0x7834);

		regVal &= (~(0x1 << (19 + i)));

		reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);

		regVal |= (reg_field << (19 + i));

		REG_WRITE(ah, 0x7834, regVal);

	}



	REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);

	udelay(1);

	reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);

	offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);

	offs_0   = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);



	offset = (offs_6_1<<1) | offs_0;

	offset = offset - 0;

	offs_6_1 = offset>>1;

	offs_0 = offset & 1;



	REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);

	REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);



	regVal = REG_READ(ah, 0x7834);

	regVal |= 0x1;

	REG_WRITE(ah, 0x7834, regVal);

	regVal = REG_READ(ah, 0x9808);

	regVal &= (~(0x1 << 27));

	REG_WRITE(ah, 0x9808, regVal);



	for (i = 0; i < ARRAY_SIZE(regList); i++)

		REG_WRITE(ah, regList[i][0], regList[i][1]);



	REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);



	if (AR_SREV_9285_11(ah))

		REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);



}



bool ath9k_hw_init_cal(struct ath_hal *ah,

		       struct ath9k_channel *chan)

{
@@ -835,6 +930,9 @@ bool ath9k_hw_init_cal(struct ath_hal *ah, 
		return false;

	}



	if (AR_SREV_9285(ah) && AR_SREV_9285_11_OR_LATER(ah))

		ath9k_hw_9285_pa_cal(ah);



	REG_WRITE(ah, AR_PHY_AGC_CONTROL,

		  REG_READ(ah, AR_PHY_AGC_CONTROL) |

		  AR_PHY_AGC_CONTROL_NF);

drivers/net/wireless/ath9k/eeprom.c

+1597 −383

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/wireless/ath9k/hw.c

+70 −20
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type); 
static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,

			      enum ath9k_ht_macmode macmode);

static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,

			      struct ar5416_eeprom *pEepData,

			      struct ar5416_eeprom_def *pEepData,

			      u32 reg, u32 value);

static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);

static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
@@ -392,6 +392,8 @@ static const char *ath9k_hw_devname(u16 devid) 
	case AR9280_DEVID_PCI:

	case AR9280_DEVID_PCIE:

		return "Atheros 9280";

	case AR9285_DEVID_PCIE:

		return "Atheros 9285";

	}



	return NULL;
@@ -682,7 +684,7 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 
	if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&

	    (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&

	    (ah->ah_macVersion != AR_SREV_VERSION_9160) &&

	    (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {

	    (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {

		DPRINTF(ah->ah_sc, ATH_DBG_RESET,

			"Mac Chip Rev 0x%02x.%x is not supported by "

			"this driver\n", ah->ah_macVersion, ah->ah_macRev);
@@ -733,7 +735,38 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 
		"This Mac Chip Rev 0x%02x.%x is \n",

		ah->ah_macVersion, ah->ah_macRev);



	if (AR_SREV_9280_20_OR_LATER(ah)) {

	if (AR_SREV_9285_12_OR_LATER(ah)) {

		INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,

			       ARRAY_SIZE(ar9285Modes_9285_1_2), 6);

		INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,

			       ARRAY_SIZE(ar9285Common_9285_1_2), 2);



		if (ah->ah_config.pcie_clock_req) {

			INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,

			ar9285PciePhy_clkreq_off_L1_9285_1_2,

			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);

		} else {

			INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,

			ar9285PciePhy_clkreq_always_on_L1_9285_1_2,

			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),

				  2);

		}

	} else if (AR_SREV_9285_10_OR_LATER(ah)) {

		INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,

			       ARRAY_SIZE(ar9285Modes_9285), 6);

		INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,

			       ARRAY_SIZE(ar9285Common_9285), 2);



		if (ah->ah_config.pcie_clock_req) {

			INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,

			ar9285PciePhy_clkreq_off_L1_9285,

			ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);

		} else {

			INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,

			ar9285PciePhy_clkreq_always_on_L1_9285,

			ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);

		}

	} else if (AR_SREV_9280_20_OR_LATER(ah)) {

		INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,

			       ARRAY_SIZE(ar9280Modes_9280_2), 6);

		INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
@@ -843,11 +876,11 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 
		goto bad;



	/* rxgain table */

	if (AR_SREV_9280_20_OR_LATER(ah))

	if (AR_SREV_9280_20(ah))

		ath9k_hw_init_rxgain_ini(ah);



	/* txgain table */

	if (AR_SREV_9280_20_OR_LATER(ah))

	if (AR_SREV_9280_20(ah))

		ath9k_hw_init_txgain_ini(ah);



	if (ah->ah_devid == AR9280_DEVID_PCI) {
@@ -858,7 +891,8 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, 
				u32 val = INI_RA(&ahp->ah_iniModes, i, j);



				INI_RA(&ahp->ah_iniModes, i, j) =

					ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,

					ath9k_hw_ini_fixup(ah,

							   &ahp->ah_eeprom.def,

							   reg, val);

			}

		}
@@ -1016,8 +1050,6 @@ static void ath9k_hw_init_chain_masks(struct ath_hal *ah) 
		}

	case 0x1:

	case 0x2:

		if (!AR_SREV_9280(ah))

			break;

	case 0x7:

		REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);

		REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
@@ -1162,12 +1194,10 @@ struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc, 
	case AR9160_DEVID_PCI:

	case AR9280_DEVID_PCI:

	case AR9280_DEVID_PCIE:

	case AR9285_DEVID_PCIE:

		ah = ath9k_hw_do_attach(devid, sc, mem, error);

		break;

	default:

		DPRINTF(ah->ah_sc, ATH_DBG_ANY,

			"devid=0x%x not supported.\n", devid);

		ah = NULL;

		*error = -ENXIO;

		break;

	}
@@ -1189,8 +1219,8 @@ static void ath9k_hw_override_ini(struct ath_hal *ah, 
	REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);

}



static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,

			      struct ar5416_eeprom *pEepData,

static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,

			      struct ar5416_eeprom_def *pEepData,

			      u32 reg, u32 value)

{

	struct base_eep_header *pBase = &(pEepData->baseEepHeader);
@@ -1223,6 +1253,18 @@ static u32 ath9k_hw_ini_fixup(struct ath_hal *ah, 
	return value;

}



static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,

			      struct ar5416_eeprom_def *pEepData,

			      u32 reg, u32 value)

{

	struct ath_hal_5416 *ahp = AH5416(ah);



	if (ahp->ah_eep_map == EEP_MAP_4KBITS)

		return value;

	else

		return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);

}



static int ath9k_hw_process_ini(struct ath_hal *ah,

				struct ath9k_channel *chan,

				enum ath9k_ht_macmode macmode)
@@ -1300,10 +1342,10 @@ static int ath9k_hw_process_ini(struct ath_hal *ah, 
		DO_DELAY(regWrites);

	}



	if (AR_SREV_9280_20_OR_LATER(ah))

	if (AR_SREV_9280(ah))

		REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);



	if (AR_SREV_9280_20_OR_LATER(ah))

	if (AR_SREV_9280(ah))

		REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);



	for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
@@ -1576,10 +1618,15 @@ static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan, 
			      enum ath9k_ht_macmode macmode)

{

	u32 phymode;

	u32 enableDacFifo = 0;

	struct ath_hal_5416 *ahp = AH5416(ah);



	if (AR_SREV_9285_10_OR_LATER(ah))

		enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &

					 AR_PHY_FC_ENABLE_DAC_FIFO);



	phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40

		| AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;

		| AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;



	if (IS_CHAN_HT40(chan)) {

		phymode |= AR_PHY_FC_DYN2040_EN;
@@ -2762,11 +2809,14 @@ void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore) 
	if (ah->ah_config.pcie_waen) {

		REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);

	} else {

		if (AR_SREV_9280(ah))

			REG_WRITE(ah, AR_WA, 0x0040073f);

		if (AR_SREV_9285(ah))

			REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);

		else if (AR_SREV_9280(ah))

			REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);

		else

			REG_WRITE(ah, AR_WA, 0x0000073f);

			REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);

	}



}



/**********************/
@@ -3317,7 +3367,7 @@ bool ath9k_hw_fill_cap_info(struct ath_hal *ah) 
	else

		pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;



	if (AR_SREV_9280(ah))

	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))

		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;

	else

		pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;

drivers/net/wireless/ath9k/hw.h

+130 −5
Original line number Diff line number Diff line
@@ -448,6 +448,17 @@ struct ar5416Stats { 
#define AR5416_EEP_TXGAIN_ORIGINAL         0

#define AR5416_EEP_TXGAIN_HIGH_POWER       1



#define AR5416_EEP4K_START_LOC         64

#define AR5416_EEP4K_NUM_2G_CAL_PIERS      3

#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3

#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS  3

#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS  3

#define AR5416_EEP4K_NUM_CTLS              12

#define AR5416_EEP4K_NUM_BAND_EDGES        4

#define AR5416_EEP4K_NUM_PD_GAINS          2

#define AR5416_EEP4K_PD_GAINS_IN_MASK      4

#define AR5416_EEP4K_PD_GAIN_ICEPTS        5

#define AR5416_EEP4K_MAX_CHAINS            1



enum eeprom_param {

	EEP_NFTHRESH_5,
@@ -507,6 +518,25 @@ struct base_eep_header { 
	u8 futureBase_3[25];

} __packed;



struct base_eep_header_4k {

	u16 length;

	u16 checksum;

	u16 version;

	u8 opCapFlags;

	u8 eepMisc;

	u16 regDmn[2];

	u8 macAddr[6];

	u8 rxMask;

	u8 txMask;

	u16 rfSilent;

	u16 blueToothOptions;

	u16 deviceCap;

	u32 binBuildNumber;

	u8 deviceType;

	u8 futureBase[1];

} __packed;





struct spur_chan {

	u16 spurChan;

	u8 spurRangeLow;
@@ -559,11 +589,58 @@ struct modal_eep_header { 
	struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];

} __packed;



struct modal_eep_4k_header {

    u32  antCtrlChain[AR5416_EEP4K_MAX_CHAINS];

    u32  antCtrlCommon;

    u8   antennaGainCh[AR5416_EEP4K_MAX_CHAINS];

    u8   switchSettling;

    u8   txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];

    u8   rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];

    u8   adcDesiredSize;

    u8   pgaDesiredSize;

    u8   xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];

    u8   txEndToXpaOff;

    u8   txEndToRxOn;

    u8   txFrameToXpaOn;

    u8   thresh62;

    u8   noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];

    u8   xpdGain;

    u8   xpd;

    u8   iqCalICh[AR5416_EEP4K_MAX_CHAINS];

    u8   iqCalQCh[AR5416_EEP4K_MAX_CHAINS];

    u8   pdGainOverlap;

    u8   ob_01;

    u8   db1_01;

    u8   xpaBiasLvl;

    u8   txFrameToDataStart;

    u8   txFrameToPaOn;

    u8   ht40PowerIncForPdadc;

    u8   bswAtten[AR5416_EEP4K_MAX_CHAINS];

    u8   bswMargin[AR5416_EEP4K_MAX_CHAINS];

    u8   swSettleHt40;

    u8   xatten2Db[AR5416_EEP4K_MAX_CHAINS];

    u8   xatten2Margin[AR5416_EEP4K_MAX_CHAINS];

    u8   db2_01;

    u8   version;

    u16  ob_234;

    u16  db1_234;

    u16  db2_234;

    u8   futureModal[4];



    struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];

} __packed;





struct cal_data_per_freq {

	u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];

	u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];

} __packed;



struct cal_data_per_freq_4k {

	u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];

	u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];

} __packed;



struct cal_target_power_leg {

	u8 bChannel;

	u8 tPow2x[4];
@@ -574,6 +651,7 @@ struct cal_target_power_ht { 
	u8 tPow2x[8];

} __packed;





#ifdef __BIG_ENDIAN_BITFIELD

struct cal_ctl_edges {

	u8 bChannel;
@@ -591,7 +669,12 @@ struct cal_ctl_data { 
	ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];

} __packed;



struct ar5416_eeprom {

struct cal_ctl_data_4k {

	struct cal_ctl_edges

	ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];

} __packed;



struct ar5416_eeprom_def {

	struct base_eep_header baseEepHeader;

	u8 custData[64];

	struct modal_eep_header modalHeader[2];
@@ -620,6 +703,26 @@ struct ar5416_eeprom { 
	u8 padding;

} __packed;



struct ar5416_eeprom_4k {

	struct base_eep_header_4k baseEepHeader;

	u8 custData[20];

	struct modal_eep_4k_header modalHeader;

	u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];

	struct cal_data_per_freq_4k

	calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];

	struct cal_target_power_leg

	calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];

	struct cal_target_power_leg

	calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];

	struct cal_target_power_ht

	calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];

	struct cal_target_power_ht

	calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];

	u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];

	struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];

	u8 padding;

} __packed;



struct ar5416IniArray {

	u32 *ia_array;

	u32 ia_rows;
@@ -687,9 +790,22 @@ struct hal_cal_list { 
	struct hal_cal_list *calNext;

};



/*

 * Enum to indentify the eeprom mappings

 */

enum hal_eep_map {

	EEP_MAP_DEFAULT = 0x0,

	EEP_MAP_4KBITS,

	EEP_MAP_MAX

};





struct ath_hal_5416 {

	struct ath_hal ah;

	struct ar5416_eeprom ah_eeprom;

	union {

		struct ar5416_eeprom_def def;

		struct ar5416_eeprom_4k map4k;

	} ah_eeprom;

	struct ar5416Stats ah_stats;

	struct ath9k_tx_queue_info ah_txq[ATH9K_NUM_TX_QUEUES];

	void __iomem *ah_cal_mem;
@@ -813,6 +929,8 @@ struct ath_hal_5416 { 
	struct ar5416IniArray ah_iniModesAdditional;

	struct ar5416IniArray ah_iniModesRxGain;

	struct ar5416IniArray ah_iniModesTxGain;

	/* To indicate EEPROM mapping used */

	enum hal_eep_map ah_eep_map;

};

#define AH5416(_ah) ((struct ath_hal_5416 *)(_ah))
@@ -854,13 +972,20 @@ struct ath_hal_5416 { 
	(AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200

#define AR5416_EEPROM_MAX           0xae0

#define ar5416_get_eep_ver(_ahp) \

	(((_ahp)->ah_eeprom.baseEepHeader.version >> 12) & 0xF)

	(((_ahp)->ah_eeprom.def.baseEepHeader.version >> 12) & 0xF)

#define ar5416_get_eep_rev(_ahp) \

	(((_ahp)->ah_eeprom.baseEepHeader.version) & 0xFFF)

	(((_ahp)->ah_eeprom.def.baseEepHeader.version) & 0xFFF)

#define ar5416_get_ntxchains(_txchainmask) \

	(((_txchainmask >> 2) & 1) + \

		((_txchainmask >> 1) & 1) + (_txchainmask & 1))



/* EEPROM 4K bit map definations */

#define ar5416_get_eep4k_ver(_ahp)   \

    (((_ahp)->ah_eeprom.map4k.baseEepHeader.version >> 12) & 0xF)

#define ar5416_get_eep4k_rev(_ahp)   \

    (((_ahp)->ah_eeprom.map4k.baseEepHeader.version) & 0xFFF)





#ifdef __BIG_ENDIAN

#define AR5416_EEPROM_MAGIC 0x5aa5

#else