drm/amd/powerplay: fix spelling typo in function name (e71b7ae6) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -470,7 +470,7 @@ uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr)
	* SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.		* SET_VOLTAGE_TYPE_ASIC_MVDDC, SET_VOLTAGE_TYPE_ASIC_MVDDQ.
	* voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE		* voltage_mode is one of ATOM_SET_VOLTAGE, ATOM_SET_VOLTAGE_PHASE
	*/		*/
	bool atomctrl_is_voltage_controled_by_gpio_v3(		bool atomctrl_is_voltage_controlled_by_gpio_v3(
	struct pp_hwmgr *hwmgr,		struct pp_hwmgr *hwmgr,
	uint8_t voltage_type,		uint8_t voltage_type,
	uint8_t voltage_mode)		uint8_t voltage_mode)

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -291,7 +291,7 @@ extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr);
	extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param mpll_param, bool strobe_mode);		extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param mpll_param, bool strobe_mode);
	extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi dividers);		extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi dividers);
	extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi dividers);		extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi dividers);
	extern bool atomctrl_is_voltage_controled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);		extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode);
	extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table voltage_table);		extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table voltage_table);
	extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,		extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr,
	uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);		uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param);

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+6 −6

drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c

+0 −11

Original line number	Original line	Diff line number	Diff line
	@@ -398,11 +398,6 @@ static int fiji_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
	return 0;		return 0;
	}		}

	static int fiji_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
	{
	return 0;
	}

	static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)		static int fiji_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
	{		{
	struct fiji_smumgr smu_data = (struct fiji_smumgr )(hwmgr->smumgr->backend);		struct fiji_smumgr smu_data = (struct fiji_smumgr )(hwmgr->smumgr->backend);
	@@ -472,12 +467,6 @@ static int fiji_populate_pm_fuses(struct pp_hwmgr *hwmgr)
	"Attempt to populate GnbLPML Failed!",		"Attempt to populate GnbLPML Failed!",
	return -EINVAL);		return -EINVAL);

	/* DW19 */
	if (fiji_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
	PP_ASSERT_WITH_CODE(false,
	"Attempt to populate GnbLPML Min and Max Vid Failed!",
	return -EINVAL);

	/* DW20 */		/* DW20 */
	if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))		if (fiji_populate_bapm_vddc_base_leakage_sidd(hwmgr))
	PP_ASSERT_WITH_CODE(false,		PP_ASSERT_WITH_CODE(false,

drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c

+5 −16

Original line number	Original line	Diff line number	Diff line
	@@ -193,11 +193,6 @@ static int iceland_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
	return 0;		return 0;
	}		}

	static int iceland_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
	{
	return 0;
	}

	static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)		static int iceland_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
	{		{
	struct iceland_smumgr smu_data = (struct iceland_smumgr )(hwmgr->smumgr->backend);		struct iceland_smumgr smu_data = (struct iceland_smumgr )(hwmgr->smumgr->backend);
	@@ -317,12 +312,6 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
	"Attempt to populate GnbLPML Failed!",		"Attempt to populate GnbLPML Failed!",
	return -EINVAL);		return -EINVAL);

	/* DW17 */
	if (iceland_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
	PP_ASSERT_WITH_CODE(false,
	"Attempt to populate GnbLPML Min and Max Vid Failed!",
	return -EINVAL);

	/* DW18 */		/* DW18 */
	if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))		if (iceland_populate_bapm_vddc_base_leakage_sidd(hwmgr))
	PP_ASSERT_WITH_CODE(false,		PP_ASSERT_WITH_CODE(false,
	@@ -339,7 +328,7 @@ static int iceland_populate_pm_fuses(struct pp_hwmgr *hwmgr)
	return 0;		return 0;
	}		}

	static int iceland_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,		static int iceland_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
	struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,		struct phm_clock_voltage_dependency_table *allowed_clock_voltage_table,
	uint32_t clock, uint32_t *vol)		uint32_t clock, uint32_t *vol)
	{		{
	@@ -749,7 +738,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
	result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);		result = iceland_calculate_sclk_params(hwmgr, engine_clock, graphic_level);

	/* populate graphics levels*/		/* populate graphics levels*/
	result = iceland_get_dependecy_volt_by_clk(hwmgr,		result = iceland_get_dependency_volt_by_clk(hwmgr,
	hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,		hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
	&graphic_level->MinVddc);		&graphic_level->MinVddc);
	PP_ASSERT_WITH_CODE((0 == result),		PP_ASSERT_WITH_CODE((0 == result),
	@@ -1104,7 +1093,7 @@ static int iceland_populate_single_memory_level(
	uint32_t mclk_strobe_mode_threshold = 40000;		uint32_t mclk_strobe_mode_threshold = 40000;

	if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {		if (hwmgr->dyn_state.vddc_dependency_on_mclk != NULL) {
	result = iceland_get_dependecy_volt_by_clk(hwmgr,		result = iceland_get_dependency_volt_by_clk(hwmgr,
	hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);		hwmgr->dyn_state.vddc_dependency_on_mclk, memory_clock, &memory_level->MinVddc);
	PP_ASSERT_WITH_CODE((0 == result),		PP_ASSERT_WITH_CODE((0 == result),
	"can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);		"can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
	@@ -1113,7 +1102,7 @@ static int iceland_populate_single_memory_level(
	if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {		if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) {
	memory_level->MinVddci = memory_level->MinVddc;		memory_level->MinVddci = memory_level->MinVddc;
	} else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {		} else if (NULL != hwmgr->dyn_state.vddci_dependency_on_mclk) {
	result = iceland_get_dependecy_volt_by_clk(hwmgr,		result = iceland_get_dependency_volt_by_clk(hwmgr,
	hwmgr->dyn_state.vddci_dependency_on_mclk,		hwmgr->dyn_state.vddci_dependency_on_mclk,
	memory_clock,		memory_clock,
	&memory_level->MinVddci);		&memory_level->MinVddci);
	@@ -1776,7 +1765,7 @@ static int iceland_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);		CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_PkgPwrLimit);
	CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);		CONVERT_FROM_HOST_TO_SMC_US(dpm_table->PPM_TemperatureLimit);

	dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bamp_temp_gradient);		dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
	def1 = defaults->bapmti_r;		def1 = defaults->bapmti_r;
	def2 = defaults->bapmti_rc;		def2 = defaults->bapmti_rc;

Original line number	Original line	Diff line number	Diff line
	@@ -1392,13 +1392,13 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
	}		}

	data->fast_watermark_threshold = 100;		data->fast_watermark_threshold = 100;
	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
	VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))		VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
	data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;		data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	PHM_PlatformCaps_ControlVDDGFX)) {		PHM_PlatformCaps_ControlVDDGFX)) {
	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
	VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {		VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) {
	data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;		data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
	}		}
	@@ -1406,10 +1406,10 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	PHM_PlatformCaps_EnableMVDDControl)) {		PHM_PlatformCaps_EnableMVDDControl)) {
	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
	VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))		VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
	data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;		data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
	else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,		else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
	VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))		VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
	data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;		data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
	}		}
	@@ -1421,10 +1421,10 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)

	if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,		if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
	PHM_PlatformCaps_ControlVDDCI)) {		PHM_PlatformCaps_ControlVDDCI)) {
	if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,		if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
	VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))		VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
	data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;		data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO;
	else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr,		else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr,
	VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))		VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
	data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;		data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2;
	}		}