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Commit e6fff4aa authored by Thierry Reding's avatar Thierry Reding
Browse files

gpu: host1x: Add Tegra124 support 



Tegra124 has 192 syncpoints whereas its predecessors had 32 syncpoints.
This required changes to the hardware register layout.

Signed-off-by: default avatarArto Merilainen <amerilainen@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 23a0e27a

drivers/gpu/host1x/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ host1x-y = \ 
	debug.o \

	mipi.o \

	hw/host1x01.o \

	hw/host1x02.o

	hw/host1x02.o \

	hw/host1x04.o



obj-$(CONFIG_TEGRA_HOST1X) += host1x.o

drivers/gpu/host1x/dev.c

+11 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include "debug.h"

#include "hw/host1x01.h"

#include "hw/host1x02.h"

#include "hw/host1x04.h"



void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)

{
@@ -77,7 +78,17 @@ static const struct host1x_info host1x02_info = { 
	.sync_offset = 0x3000,

};



static const struct host1x_info host1x04_info = {

	.nb_channels = 12,

	.nb_pts = 192,

	.nb_mlocks = 16,

	.nb_bases = 64,

	.init = host1x04_init,

	.sync_offset = 0x2100,

};



static struct of_device_id host1x_of_match[] = {

	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },

	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },

	{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },

	{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },

drivers/gpu/host1x/hw/host1x04.c

0 → 100644
+42 −0
Original line number Diff line number Diff line 
/*

 * Host1x init for Tegra124 SoCs

 *

 * Copyright (c) 2013 NVIDIA Corporation.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



/* include hw specification */

#include "host1x04.h"

#include "host1x04_hardware.h"



/* include code */

#include "cdma_hw.c"

#include "channel_hw.c"

#include "debug_hw.c"

#include "intr_hw.c"

#include "syncpt_hw.c"



#include "../dev.h"



int host1x04_init(struct host1x *host)

{

	host->channel_op = &host1x_channel_ops;

	host->cdma_op = &host1x_cdma_ops;

	host->cdma_pb_op = &host1x_pushbuffer_ops;

	host->syncpt_op = &host1x_syncpt_ops;

	host->intr_op = &host1x_intr_ops;

	host->debug_op = &host1x_debug_ops;



	return 0;

}

drivers/gpu/host1x/hw/host1x04.h

0 → 100644
+26 −0
Original line number Diff line number Diff line 
/*

 * Host1x init for Tegra124 SoCs

 *

 * Copyright (c) 2013 NVIDIA Corporation.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef HOST1X_HOST1X04_H

#define HOST1X_HOST1X04_H



struct host1x;



int host1x04_init(struct host1x *host);



#endif

drivers/gpu/host1x/hw/host1x04_hardware.h

0 → 100644
+142 −0
Original line number Diff line number Diff line 
/*

 * Tegra host1x Register Offsets for Tegra124

 *

 * Copyright (c) 2010-2013 NVIDIA Corporation.

 *

 * This program is free software; you can redistribute it and/or modify it

 * under the terms and conditions of the GNU General Public License,

 * version 2, as published by the Free Software Foundation.

 *

 * This program is distributed in the hope it will be useful, but WITHOUT

 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

 * more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */



#ifndef __HOST1X_HOST1X04_HARDWARE_H

#define __HOST1X_HOST1X04_HARDWARE_H



#include <linux/types.h>

#include <linux/bitops.h>



#include "hw_host1x04_channel.h"

#include "hw_host1x04_sync.h"

#include "hw_host1x04_uclass.h"



static inline u32 host1x_class_host_wait_syncpt(

	unsigned indx, unsigned threshold)

{

	return host1x_uclass_wait_syncpt_indx_f(indx)

		| host1x_uclass_wait_syncpt_thresh_f(threshold);

}



static inline u32 host1x_class_host_load_syncpt_base(

	unsigned indx, unsigned threshold)

{

	return host1x_uclass_load_syncpt_base_base_indx_f(indx)

		| host1x_uclass_load_syncpt_base_value_f(threshold);

}



static inline u32 host1x_class_host_wait_syncpt_base(

	unsigned indx, unsigned base_indx, unsigned offset)

{

	return host1x_uclass_wait_syncpt_base_indx_f(indx)

		| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)

		| host1x_uclass_wait_syncpt_base_offset_f(offset);

}



static inline u32 host1x_class_host_incr_syncpt_base(

	unsigned base_indx, unsigned offset)

{

	return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)

		| host1x_uclass_incr_syncpt_base_offset_f(offset);

}



static inline u32 host1x_class_host_incr_syncpt(

	unsigned cond, unsigned indx)

{

	return host1x_uclass_incr_syncpt_cond_f(cond)

		| host1x_uclass_incr_syncpt_indx_f(indx);

}



static inline u32 host1x_class_host_indoff_reg_write(

	unsigned mod_id, unsigned offset, bool auto_inc)

{

	u32 v = host1x_uclass_indoff_indbe_f(0xf)

		| host1x_uclass_indoff_indmodid_f(mod_id)

		| host1x_uclass_indoff_indroffset_f(offset);

	if (auto_inc)

		v |= host1x_uclass_indoff_autoinc_f(1);

	return v;

}



static inline u32 host1x_class_host_indoff_reg_read(

	unsigned mod_id, unsigned offset, bool auto_inc)

{

	u32 v = host1x_uclass_indoff_indmodid_f(mod_id)

		| host1x_uclass_indoff_indroffset_f(offset)

		| host1x_uclass_indoff_rwn_read_v();

	if (auto_inc)

		v |= host1x_uclass_indoff_autoinc_f(1);

	return v;

}



/* cdma opcodes */

static inline u32 host1x_opcode_setclass(

	unsigned class_id, unsigned offset, unsigned mask)

{

	return (0 << 28) | (offset << 16) | (class_id << 6) | mask;

}



static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)

{

	return (1 << 28) | (offset << 16) | count;

}



static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)

{

	return (2 << 28) | (offset << 16) | count;

}



static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)

{

	return (3 << 28) | (offset << 16) | mask;

}



static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)

{

	return (4 << 28) | (offset << 16) | value;

}



static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)

{

	return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),

		host1x_class_host_incr_syncpt(cond, indx));

}



static inline u32 host1x_opcode_restart(unsigned address)

{

	return (5 << 28) | (address >> 4);

}



static inline u32 host1x_opcode_gather(unsigned count)

{

	return (6 << 28) | count;

}



static inline u32 host1x_opcode_gather_nonincr(unsigned offset,	unsigned count)

{

	return (6 << 28) | (offset << 16) | BIT(15) | count;

}



static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)

{

	return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;

}



#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)



#endif