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Commit e6bbe1d0 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge 4.2-rc6 into usb-next 



We want the USB fixes in here as well.

Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parents 7e34d70a f7644cbf

Documentation/devicetree/bindings/dma/apm-xgene-dma.txt

+1 −1
Original line number Diff line number Diff line
@@ -35,7 +35,7 @@ Example: 
			device_type = "dma";

			reg = <0x0 0x1f270000 0x0 0x10000>,

			      <0x0 0x1f200000 0x0 0x10000>,

			      <0x0 0x1b008000 0x0 0x2000>,

			      <0x0 0x1b000000 0x0 0x400000>,

			      <0x0 0x1054a000 0x0 0x100>;

			interrupts = <0x0 0x82 0x4>,

				     <0x0 0xb8 0x4>,

Documentation/devicetree/bindings/phy/ti-phy.txt

+16 −0
Original line number Diff line number Diff line
@@ -82,6 +82,9 @@ Optional properties: 
 - id: If there are multiple instance of the same type, in order to

   differentiate between each instance "id" can be used (e.g., multi-lane PCIe

   PHY). If "id" is not provided, it is set to default value of '1'.

 - syscon-pllreset: Handle to system control region that contains the

   CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0

   register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.



This is usually a subnode of ocp2scp to which it is connected.
@@ -100,3 +103,16 @@ usb3phy@4a084400 { 
			"sysclk",

			"refclk";

};



sata_phy: phy@4A096000 {

	compatible = "ti,phy-pipe3-sata";

	reg = <0x4A096000 0x80>, /* phy_rx */

	      <0x4A096400 0x64>, /* phy_tx */

	      <0x4A096800 0x40>; /* pll_ctrl */

	reg-names = "phy_rx", "phy_tx", "pll_ctrl";

	ctrl-module = <&omap_control_sata>;

	clocks = <&sys_clkin1>, <&sata_ref_clk>;

	clock-names = "sysclk", "refclk";

	syscon-pllreset = <&scm_conf 0x3fc>;

	#phy-cells = <0>;

};

Documentation/devicetree/bindings/sound/mt8173-max98090.txt

+2 −0
Original line number Diff line number Diff line
@@ -3,11 +3,13 @@ MT8173 with MAX98090 CODEC 
Required properties:

- compatible : "mediatek,mt8173-max98090"

- mediatek,audio-codec: the phandle of the MAX98090 audio codec

- mediatek,platform: the phandle of MT8173 ASoC platform



Example:



	sound {

		compatible = "mediatek,mt8173-max98090";

		mediatek,audio-codec = <&max98090>;

		mediatek,platform = <&afe>;

	};

Documentation/devicetree/bindings/sound/mt8173-rt5650-rt5676.txt

+2 −0
Original line number Diff line number Diff line
@@ -3,11 +3,13 @@ MT8173 with RT5650 RT5676 CODECS 
Required properties:

- compatible : "mediatek,mt8173-rt5650-rt5676"

- mediatek,audio-codec: the phandles of rt5650 and rt5676 codecs

- mediatek,platform: the phandle of MT8173 ASoC platform



Example:



	sound {

		compatible = "mediatek,mt8173-rt5650-rt5676";

		mediatek,audio-codec = <&rt5650 &rt5676>;

		mediatek,platform = <&afe>;

	};

Documentation/devicetree/bindings/spi/spi-ath79.txt

+3 −3
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller 
Required properties:

- compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.

- reg: Base address and size of the controllers memory area

- clocks: phandle to the AHB clock.

- clocks: phandle of the AHB clock.

- clock-names: has to be "ahb".

- #address-cells: <1>, as required by generic SPI binding.

- #size-cells: <0>, also as required by generic SPI binding.
@@ -12,9 +12,9 @@ Child nodes as per the generic SPI binding. 


Example:



	spi@1F000000 {

	spi@1f000000 {

		compatible = "qca,ar9132-spi", "qca,ar7100-spi";

		reg = <0x1F000000 0x10>;

		reg = <0x1f000000 0x10>;



		clocks = <&pll 2>;

		clock-names = "ahb";