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Commit e6b9a6c8 authored by Mario Kleiner's avatar Mario Kleiner Committed by Alex Deucher
Browse files

drm/radeon: Make display watermark calculations more accurate 



Avoid big roundoff errors in scanline/hactive durations for
high pixel clocks, especially for >= 500 Mhz, and thereby
program more accurate display fifo watermarks.

This is a port of the corresponding amdgpu patch.

Implemented for DCE 4,6,8.
Tested on Evergreen/DCE-4 with Radeon HD-5770.

Signed-off-by: default avatarMario Kleiner <mario.kleiner.de@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ae45bbc2

drivers/gpu/drm/radeon/cik.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -9261,14 +9261,14 @@ static void dce8_program_watermarks(struct radeon_device *rdev, 
{

{

	struct drm_display_mode *mode = &radeon_crtc->base.mode;

	struct drm_display_mode *mode = &radeon_crtc->base.mode;

	struct dce8_wm_params wm_low, wm_high;

	struct dce8_wm_params wm_low, wm_high;

	u32 pixel_period;

	u32 active_time;

	u32 line_time = 0;

	u32 line_time = 0;

	u32 latency_watermark_a = 0, latency_watermark_b = 0;

	u32 latency_watermark_a = 0, latency_watermark_b = 0;

	u32 tmp, wm_mask;

	u32 tmp, wm_mask;





	if (radeon_crtc->base.enabled && num_heads && mode) {

	if (radeon_crtc->base.enabled && num_heads && mode) {

		pixel_period = 1000000 / (u32)mode->clock;

		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;

		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);

		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);





		/* watermark for high clocks */

		/* watermark for high clocks */

		if ((rdev->pm.pm_method == PM_METHOD_DPM) &&

		if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
@@ -9284,7 +9284,7 @@ static void dce8_program_watermarks(struct radeon_device *rdev, 




		wm_high.disp_clk = mode->clock;

		wm_high.disp_clk = mode->clock;

		wm_high.src_width = mode->crtc_hdisplay;

		wm_high.src_width = mode->crtc_hdisplay;

		wm_high.active_time = mode->crtc_hdisplay * pixel_period;

		wm_high.active_time = active_time;

		wm_high.blank_time = line_time - wm_high.active_time;

		wm_high.blank_time = line_time - wm_high.active_time;

		wm_high.interlaced = false;

		wm_high.interlaced = false;

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -9324,7 +9324,7 @@ static void dce8_program_watermarks(struct radeon_device *rdev, 




		wm_low.disp_clk = mode->clock;

		wm_low.disp_clk = mode->clock;

		wm_low.src_width = mode->crtc_hdisplay;

		wm_low.src_width = mode->crtc_hdisplay;

		wm_low.active_time = mode->crtc_hdisplay * pixel_period;

		wm_low.active_time = active_time;

		wm_low.blank_time = line_time - wm_low.active_time;

		wm_low.blank_time = line_time - wm_low.active_time;

		wm_low.interlaced = false;

		wm_low.interlaced = false;

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)

drivers/gpu/drm/radeon/evergreen.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -2255,7 +2255,7 @@ static void evergreen_program_watermarks(struct radeon_device *rdev, 
	struct drm_display_mode *mode = &radeon_crtc->base.mode;

	struct drm_display_mode *mode = &radeon_crtc->base.mode;

	struct evergreen_wm_params wm_low, wm_high;

	struct evergreen_wm_params wm_low, wm_high;

	u32 dram_channels;

	u32 dram_channels;

	u32 pixel_period;

	u32 active_time;

	u32 line_time = 0;

	u32 line_time = 0;

	u32 latency_watermark_a = 0, latency_watermark_b = 0;

	u32 latency_watermark_a = 0, latency_watermark_b = 0;

	u32 priority_a_mark = 0, priority_b_mark = 0;

	u32 priority_a_mark = 0, priority_b_mark = 0;
@@ -2266,8 +2266,8 @@ static void evergreen_program_watermarks(struct radeon_device *rdev, 
	fixed20_12 a, b, c;

	fixed20_12 a, b, c;





	if (radeon_crtc->base.enabled && num_heads && mode) {

	if (radeon_crtc->base.enabled && num_heads && mode) {

		pixel_period = 1000000 / (u32)mode->clock;

		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;

		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);

		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);

		priority_a_cnt = 0;

		priority_a_cnt = 0;

		priority_b_cnt = 0;

		priority_b_cnt = 0;

		dram_channels = evergreen_get_number_of_dram_channels(rdev);

		dram_channels = evergreen_get_number_of_dram_channels(rdev);
@@ -2285,7 +2285,7 @@ static void evergreen_program_watermarks(struct radeon_device *rdev, 




		wm_high.disp_clk = mode->clock;

		wm_high.disp_clk = mode->clock;

		wm_high.src_width = mode->crtc_hdisplay;

		wm_high.src_width = mode->crtc_hdisplay;

		wm_high.active_time = mode->crtc_hdisplay * pixel_period;

		wm_high.active_time = active_time;

		wm_high.blank_time = line_time - wm_high.active_time;

		wm_high.blank_time = line_time - wm_high.active_time;

		wm_high.interlaced = false;

		wm_high.interlaced = false;

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -2312,7 +2312,7 @@ static void evergreen_program_watermarks(struct radeon_device *rdev, 




		wm_low.disp_clk = mode->clock;

		wm_low.disp_clk = mode->clock;

		wm_low.src_width = mode->crtc_hdisplay;

		wm_low.src_width = mode->crtc_hdisplay;

		wm_low.active_time = mode->crtc_hdisplay * pixel_period;

		wm_low.active_time = active_time;

		wm_low.blank_time = line_time - wm_low.active_time;

		wm_low.blank_time = line_time - wm_low.active_time;

		wm_low.interlaced = false;

		wm_low.interlaced = false;

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)

drivers/gpu/drm/radeon/si.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -2274,7 +2274,7 @@ static void dce6_program_watermarks(struct radeon_device *rdev, 
	struct drm_display_mode *mode = &radeon_crtc->base.mode;

	struct drm_display_mode *mode = &radeon_crtc->base.mode;

	struct dce6_wm_params wm_low, wm_high;

	struct dce6_wm_params wm_low, wm_high;

	u32 dram_channels;

	u32 dram_channels;

	u32 pixel_period;

	u32 active_time;

	u32 line_time = 0;

	u32 line_time = 0;

	u32 latency_watermark_a = 0, latency_watermark_b = 0;

	u32 latency_watermark_a = 0, latency_watermark_b = 0;

	u32 priority_a_mark = 0, priority_b_mark = 0;

	u32 priority_a_mark = 0, priority_b_mark = 0;
@@ -2284,8 +2284,8 @@ static void dce6_program_watermarks(struct radeon_device *rdev, 
	fixed20_12 a, b, c;

	fixed20_12 a, b, c;





	if (radeon_crtc->base.enabled && num_heads && mode) {

	if (radeon_crtc->base.enabled && num_heads && mode) {

		pixel_period = 1000000 / (u32)mode->clock;

		active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;

		line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);

		line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);

		priority_a_cnt = 0;

		priority_a_cnt = 0;

		priority_b_cnt = 0;

		priority_b_cnt = 0;
@@ -2307,7 +2307,7 @@ static void dce6_program_watermarks(struct radeon_device *rdev, 




		wm_high.disp_clk = mode->clock;

		wm_high.disp_clk = mode->clock;

		wm_high.src_width = mode->crtc_hdisplay;

		wm_high.src_width = mode->crtc_hdisplay;

		wm_high.active_time = mode->crtc_hdisplay * pixel_period;

		wm_high.active_time = active_time;

		wm_high.blank_time = line_time - wm_high.active_time;

		wm_high.blank_time = line_time - wm_high.active_time;

		wm_high.interlaced = false;

		wm_high.interlaced = false;

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
@@ -2334,7 +2334,7 @@ static void dce6_program_watermarks(struct radeon_device *rdev, 




		wm_low.disp_clk = mode->clock;

		wm_low.disp_clk = mode->clock;

		wm_low.src_width = mode->crtc_hdisplay;

		wm_low.src_width = mode->crtc_hdisplay;

		wm_low.active_time = mode->crtc_hdisplay * pixel_period;

		wm_low.active_time = active_time;

		wm_low.blank_time = line_time - wm_low.active_time;

		wm_low.blank_time = line_time - wm_low.active_time;

		wm_low.interlaced = false;

		wm_low.interlaced = false;

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)

		if (mode->flags & DRM_MODE_FLAG_INTERLACE)