Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e6ab9a20 authored by H. Peter Anvin's avatar H. Peter Anvin
Browse files

Merge commit '7ed6fb9b' into x86/espfix 



Merge in Linus' tree with:

fa81511b x86-64, modify_ldt: Make support for 16-bit segments a runtime option

... reverted, to avoid a conflict.  This commit is no longer necessary
with the proper fix in place.

Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parents 34273f41 7ed6fb9b

Documentation/devicetree/bindings/arm/arch_timer.txt

+3 −0
Original line number Diff line number Diff line
@@ -19,6 +19,9 @@ to deliver its interrupts via SPIs. 


- clock-frequency : The frequency of the main counter, in Hz. Optional.



- always-on : a boolean property. If present, the timer is powered through an

  always-on power domain, therefore it never loses context.



Example:



	timer {

Documentation/devicetree/bindings/ata/apm-xgene.txt

+3 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ Required properties: 
  * "sata-phy" for the SATA 6.0Gbps PHY



Optional properties:

- dma-coherent		: Present if dma operations are coherent

- status		: Shall be "ok" if enabled or "disabled" if disabled.

			  Default is "ok".
@@ -55,6 +56,7 @@ Example: 
			      <0x0 0x1f22e000 0x0 0x1000>,

			      <0x0 0x1f227000 0x0 0x1000>;

			interrupts = <0x0 0x87 0x4>;

			dma-coherent;

			status = "ok";

			clocks = <&sataclk 0>;

			phys = <&phy2 0>;
@@ -69,6 +71,7 @@ Example: 
			      <0x0 0x1f23e000 0x0 0x1000>,

			      <0x0 0x1f237000 0x0 0x1000>;

			interrupts = <0x0 0x88 0x4>;

			dma-coherent;

			status = "ok";

			clocks = <&sataclk 0>;

			phys = <&phy3 0>;

Documentation/devicetree/bindings/clock/at91-clock.txt

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ Required properties for PMC node: 
- interrupt-controller : tell that the PMC is an interrupt controller.

- #interrupt-cells : must be set to 1. The first cell encodes the interrupt id,

	and reflect the bit position in the PMC_ER/DR/SR registers.

	You can use the dt macros defined in dt-bindings/clk/at91.h.

	You can use the dt macros defined in dt-bindings/clock/at91.h.

	0 (AT91_PMC_MOSCS) -> main oscillator ready

	1 (AT91_PMC_LOCKA) -> PLL A ready

	2 (AT91_PMC_LOCKB) -> PLL B ready

Documentation/devicetree/bindings/dma/ti-edma.txt

+2 −2
Original line number Diff line number Diff line
@@ -29,6 +29,6 @@ edma: edma@49000000 { 
	dma-channels = <64>;

	ti,edma-regions = <4>;

	ti,edma-slots = <256>;

	ti,edma-xbar-event-map = <1 12

	ti,edma-xbar-event-map = /bits/ 16 <1 12

					    2 13>;

};

Documentation/devicetree/bindings/net/arc_emac.txt

+10 −2
Original line number Diff line number Diff line
@@ -4,11 +4,15 @@ Required properties: 
- compatible: Should be "snps,arc-emac"

- reg: Address and length of the register set for the device

- interrupts: Should contain the EMAC interrupts

- clock-frequency: CPU frequency. It is needed to calculate and set polling

period of EMAC.

- max-speed: see ethernet.txt file in the same directory.

- phy: see ethernet.txt file in the same directory.



Clock handling:

The clock frequency is needed to calculate and set polling period of EMAC.

It must be provided by one of:

- clock-frequency: CPU frequency.

- clocks: reference to the clock supplying the EMAC.



Child nodes of the driver are the individual PHY devices connected to the

MDIO bus. They must have a "reg" property given the PHY address on the MDIO bus.
@@ -19,7 +23,11 @@ Examples: 
		reg = <0xc0fc2000 0x3c>;

		interrupts = <6>;

		mac-address = [ 00 11 22 33 44 55 ];



		clock-frequency = <80000000>;

		/* or */

		clocks = <&emac_clock>;



		max-speed = <100>;

		phy = <&phy0>;