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Commit e660df07 authored by Thierry Reding's avatar Thierry Reding
Browse files

memory: tegra: Add SWGROUP names 



Subsequent patches will add debugfs files that print the status of the
SWGROUPs. Add a new names field and complement the SoC tables with the
names of the individual SWGROUPs.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent b787f68c

drivers/memory/tegra/tegra114.c

+16 −16
Original line number Original line Diff line number Diff line
@@ -896,22 +896,22 @@ static const struct tegra_mc_client tegra114_mc_clients[] = { 
};

};





static const struct tegra_smmu_swgroup tegra114_swgroups[] = {

static const struct tegra_smmu_swgroup tegra114_swgroups[] = {

	{ .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },

	{ .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },

	{ .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },

	{ .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },

	{ .swgroup = TEGRA_SWGROUP_EPP,       .reg = 0x248 },

	{ .name = "epp",       .swgroup = TEGRA_SWGROUP_EPP,       .reg = 0x248 },

	{ .swgroup = TEGRA_SWGROUP_G2,        .reg = 0x24c },

	{ .name = "g2",        .swgroup = TEGRA_SWGROUP_G2,        .reg = 0x24c },

	{ .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },

	{ .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },

	{ .swgroup = TEGRA_SWGROUP_NV,        .reg = 0x268 },

	{ .name = "nv",        .swgroup = TEGRA_SWGROUP_NV,        .reg = 0x268 },

	{ .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },

	{ .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },

	{ .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },

	{ .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },

	{ .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },

	{ .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },

	{ .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },

	{ .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },

	{ .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },

	{ .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },

	{ .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },

	{ .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },

	{ .swgroup = TEGRA_SWGROUP_ISP,       .reg = 0x258 },

	{ .name = "isp",       .swgroup = TEGRA_SWGROUP_ISP,       .reg = 0x258 },

	{ .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },

	{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },

	{ .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },

	{ .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },

	{ .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },

	{ .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },

};

};





static void tegra114_flush_dcache(struct page *page, unsigned long offset,

static void tegra114_flush_dcache(struct page *page, unsigned long offset,

drivers/memory/tegra/tegra124.c

+23 −23
Original line number Original line Diff line number Diff line
@@ -934,29 +934,29 @@ static const struct tegra_mc_client tegra124_mc_clients[] = { 
};

};





static const struct tegra_smmu_swgroup tegra124_swgroups[] = {

static const struct tegra_smmu_swgroup tegra124_swgroups[] = {

	{ .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },

	{ .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },

	{ .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },

	{ .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },

	{ .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },

	{ .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },

	{ .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },

	{ .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },

	{ .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },

	{ .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },

	{ .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },

	{ .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },

	{ .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },

	{ .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },

	{ .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },

	{ .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },

	{ .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },

	{ .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },

	{ .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },

	{ .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },

	{ .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },

	{ .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },

	{ .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },

	{ .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },

	{ .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },

	{ .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },

	{ .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },

	{ .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },

	{ .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },

	{ .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },

	{ .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },

	{ .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },

	{ .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },

	{ .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },

	{ .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },

	{ .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },

	{ .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },

	{ .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },

	{ .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },

	{ .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },

	{ .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },

	{ .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },

	{ .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },

	{ .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },

	{ .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },

	{ .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },

};

};





#ifdef CONFIG_ARCH_TEGRA_124_SOC

#ifdef CONFIG_ARCH_TEGRA_124_SOC

drivers/memory/tegra/tegra30.c

+16 −16
Original line number Original line Diff line number Diff line
@@ -918,22 +918,22 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { 
};

};





static const struct tegra_smmu_swgroup tegra30_swgroups[] = {

static const struct tegra_smmu_swgroup tegra30_swgroups[] = {

	{ .swgroup = TEGRA_SWGROUP_DC,   .reg = 0x240 },

	{ .name = "dc",   .swgroup = TEGRA_SWGROUP_DC,   .reg = 0x240 },

	{ .swgroup = TEGRA_SWGROUP_DCB,  .reg = 0x244 },

	{ .name = "dcb",  .swgroup = TEGRA_SWGROUP_DCB,  .reg = 0x244 },

	{ .swgroup = TEGRA_SWGROUP_EPP,  .reg = 0x248 },

	{ .name = "epp",  .swgroup = TEGRA_SWGROUP_EPP,  .reg = 0x248 },

	{ .swgroup = TEGRA_SWGROUP_G2,   .reg = 0x24c },

	{ .name = "g2",   .swgroup = TEGRA_SWGROUP_G2,   .reg = 0x24c },

	{ .swgroup = TEGRA_SWGROUP_MPE,  .reg = 0x264 },

	{ .name = "mpe",  .swgroup = TEGRA_SWGROUP_MPE,  .reg = 0x264 },

	{ .swgroup = TEGRA_SWGROUP_VI,   .reg = 0x280 },

	{ .name = "vi",   .swgroup = TEGRA_SWGROUP_VI,   .reg = 0x280 },

	{ .swgroup = TEGRA_SWGROUP_AFI,  .reg = 0x238 },

	{ .name = "afi",  .swgroup = TEGRA_SWGROUP_AFI,  .reg = 0x238 },

	{ .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },

	{ .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },

	{ .swgroup = TEGRA_SWGROUP_NV,   .reg = 0x268 },

	{ .name = "nv",   .swgroup = TEGRA_SWGROUP_NV,   .reg = 0x268 },

	{ .swgroup = TEGRA_SWGROUP_NV2,  .reg = 0x26c },

	{ .name = "nv2",  .swgroup = TEGRA_SWGROUP_NV2,  .reg = 0x26c },

	{ .swgroup = TEGRA_SWGROUP_HDA,  .reg = 0x254 },

	{ .name = "hda",  .swgroup = TEGRA_SWGROUP_HDA,  .reg = 0x254 },

	{ .swgroup = TEGRA_SWGROUP_HC,   .reg = 0x250 },

	{ .name = "hc",   .swgroup = TEGRA_SWGROUP_HC,   .reg = 0x250 },

	{ .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },

	{ .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },

	{ .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },

	{ .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x278 },

	{ .swgroup = TEGRA_SWGROUP_VDE,  .reg = 0x27c },

	{ .name = "vde",  .swgroup = TEGRA_SWGROUP_VDE,  .reg = 0x27c },

	{ .swgroup = TEGRA_SWGROUP_ISP,  .reg = 0x258 },

	{ .name = "isp",  .swgroup = TEGRA_SWGROUP_ISP,  .reg = 0x258 },

};

};





static void tegra30_flush_dcache(struct page *page, unsigned long offset,

static void tegra30_flush_dcache(struct page *page, unsigned long offset,

include/soc/tegra/mc.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -40,6 +40,7 @@ struct tegra_mc_client { 
};

};





struct tegra_smmu_swgroup {

struct tegra_smmu_swgroup {

	const char *name;

	unsigned int swgroup;

	unsigned int swgroup;

	unsigned int reg;

	unsigned int reg;

};

};