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Commit e61f487f authored by Chew, Chiau Ee's avatar Chew, Chiau Ee Committed by Mark Brown
Browse files

spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI 



It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.

Signed-off-by: default avatarChew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent 01d7aafb

drivers/spi/spi-pxa2xx.c

+6 −2
Original line number Original line Diff line number Diff line
@@ -118,6 +118,7 @@ static void lpss_ssp_setup(struct driver_data *drv_data) 
	 */

	 */

	orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);

	orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);





	/* Test SPI_CS_CONTROL_SW_MODE bit enabling */

	value = orig | SPI_CS_CONTROL_SW_MODE;

	value = orig | SPI_CS_CONTROL_SW_MODE;

	writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);

	writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);

	value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);

	value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
@@ -126,10 +127,13 @@ static void lpss_ssp_setup(struct driver_data *drv_data) 
		goto detection_done;

		goto detection_done;

	}

	}





	value &= ~SPI_CS_CONTROL_SW_MODE;

	orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);



	/* Test SPI_CS_CONTROL_SW_MODE bit disabling */

	value = orig & ~SPI_CS_CONTROL_SW_MODE;

	writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);

	writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);

	value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);

	value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);

	if (value != orig) {

	if (value != (orig & ~SPI_CS_CONTROL_SW_MODE)) {

		offset = 0x800;

		offset = 0x800;

		goto detection_done;

		goto detection_done;

	}

	}