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Commit e618d306 authored by Roger He's avatar Roger He Committed by Alex Deucher
Browse files

drm/amd/amdgpu: store fragment_size in vm_manager 



adds fragment_size in the vm_manager structure and
implements hardware setup for it.

Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarRoger He <Hongbo.He@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 27c7b9ae

drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

+1 −4
Original line number Diff line number Diff line
@@ -590,11 +590,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file 
		dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;

		dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;

		dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);

		dev_info.pte_fragment_size =

			(1 << AMDGPU_LOG2_PAGES_PER_FRAG(adev)) *

			AMDGPU_GPU_PAGE_SIZE;

		dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;

		dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;



		dev_info.cu_active_number = adev->gfx.cu_info.number;

		dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;

		dev_info.ce_ram_size = adev->gfx.ce_ram_size;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+1 −3
Original line number Diff line number Diff line
@@ -1410,9 +1410,7 @@ static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params, 
	 * Userspace can support this by aligning virtual base address and

	 * allocation size to the fragment size.

	 */



	/* SI and newer are optimized for 64KB */

	unsigned pages_per_frag = AMDGPU_LOG2_PAGES_PER_FRAG(params->adev);

	unsigned pages_per_frag = params->adev->vm_manager.fragment_size;

	uint64_t frag_flags = AMDGPU_PTE_FRAG(pages_per_frag);

	uint64_t frag_align = 1 << pages_per_frag;

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

+1 −5
Original line number Diff line number Diff line
@@ -50,11 +50,6 @@ struct amdgpu_bo_list_entry; 
/* PTBs (Page Table Blocks) need to be aligned to 32K */

#define AMDGPU_VM_PTB_ALIGN_SIZE   32768



/* LOG2 number of continuous pages for the fragment field */

#define AMDGPU_LOG2_PAGES_PER_FRAG(adev) \

	((adev)->asic_type < CHIP_VEGA10 ? 4 : \

	 (adev)->vm_manager.block_size)



#define AMDGPU_PTE_VALID	(1ULL << 0)

#define AMDGPU_PTE_SYSTEM	(1ULL << 1)

#define AMDGPU_PTE_SNOOPED	(1ULL << 2)
@@ -200,6 +195,7 @@ struct amdgpu_vm_manager { 
	uint32_t				num_level;

	uint64_t				vm_size;

	uint32_t				block_size;

	uint32_t				fragment_size;

	/* vram base address for page table entry  */

	u64					vram_base_offset;

	/* vm pte handling */

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+3 −2
Original line number Diff line number Diff line
@@ -124,7 +124,7 @@ static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) 


static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)

{

	uint32_t tmp;

	uint32_t tmp, field;



	/* Setup L2 cache */

	tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
@@ -143,8 +143,9 @@ static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev) 
	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);

	WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);



	field = adev->vm_manager.fragment_size;

	tmp = mmVM_L2_CNTL3_DEFAULT;

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);

	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, L2_CACHE_BIGK_FRAGMENT_SIZE, 6);

	WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);

drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c

+6 −2
Original line number Diff line number Diff line
@@ -461,6 +461,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable) 
static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)

{

	int r, i;

	u32 field;



	if (adev->gart.robj == NULL) {

		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
@@ -488,10 +489,12 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev) 
	WREG32(mmVM_L2_CNTL2,

	       VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |

	       VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);



	field = adev->vm_manager.fragment_size;

	WREG32(mmVM_L2_CNTL3,

	       VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |

	       (4UL << VM_L2_CNTL3__BANK_SELECT__SHIFT) |

	       (4UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));

	       (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |

	       (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));

	/* setup context0 */

	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->mc.gart_start >> 12);

	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->mc.gart_end >> 12);
@@ -812,6 +815,7 @@ static int gmc_v6_0_sw_init(void *handle) 
		return r;



	amdgpu_vm_adjust_size(adev, 64);

	adev->vm_manager.fragment_size = 4;

	adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;



	adev->mc.mc_mask = 0xffffffffffULL;