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Commit e5bb8ad8 authored by H. Peter Anvin's avatar H. Peter Anvin
Browse files

x86, 386 removal: Remove CONFIG_BSWAP 



All 486+ CPUs support BSWAP, so remove the fallback 386 support
code.

Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
Link: http://lkml.kernel.org/r/1354132230-21854-5-git-send-email-hpa@linux.intel.com
parent 7ac468b1

arch/x86/Kconfig.cpu

+0 −4
Original line number Diff line number Diff line
@@ -332,10 +332,6 @@ config X86_INVLPG 
	def_bool y

	depends on X86_32



config X86_BSWAP

	def_bool y

	depends on X86_32



config X86_POPAD_OK

	def_bool y

	depends on X86_32

arch/x86/include/asm/futex.h

+0 −12
Original line number Diff line number Diff line
@@ -55,12 +55,6 @@ static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) 
	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))

		return -EFAULT;



#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP)

	/* Real i386 machines can only support FUTEX_OP_SET */

	if (op != FUTEX_OP_SET && boot_cpu_data.x86 == 3)

		return -ENOSYS;

#endif



	pagefault_disable();



	switch (op) {
@@ -118,12 +112,6 @@ static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, 
{

	int ret = 0;



#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP)

	/* Real i386 machines have no cmpxchg instruction */

	if (boot_cpu_data.x86 == 3)

		return -ENOSYS;

#endif



	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))

		return -EFAULT;

arch/x86/include/asm/swab.h

+2 −27
Original line number Diff line number Diff line
@@ -6,22 +6,7 @@ 


static inline __attribute_const__ __u32 __arch_swab32(__u32 val)

{

#ifdef __i386__

# ifdef CONFIG_X86_BSWAP

	asm("bswap %0" : "=r" (val) : "0" (val));

# else

	asm("xchgb %b0,%h0\n\t"	/* swap lower bytes	*/

	    "rorl $16,%0\n\t"	/* swap words		*/

	    "xchgb %b0,%h0"	/* swap higher bytes	*/

	    : "=q" (val)

	    : "0" (val));

# endif



#else /* __i386__ */

	asm("bswapl %0"

	    : "=r" (val)

	    : "0" (val));

#endif

	asm("bswapl %0" : "=r" (val) : "0" (val));

	return val;

}

#define __arch_swab32 __arch_swab32
@@ -37,22 +22,12 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 val) 
		__u64 u;

	} v;

	v.u = val;

# ifdef CONFIG_X86_BSWAP

	asm("bswapl %0 ; bswapl %1 ; xchgl %0,%1"

	    : "=r" (v.s.a), "=r" (v.s.b)

	    : "0" (v.s.a), "1" (v.s.b));

# else

	v.s.a = __arch_swab32(v.s.a);

	v.s.b = __arch_swab32(v.s.b);

	asm("xchgl %0,%1"

	    : "=r" (v.s.a), "=r" (v.s.b)

	    : "0" (v.s.a), "1" (v.s.b));

# endif

	return v.u;

#else /* __i386__ */

	asm("bswapq %0"

	    : "=r" (val)

	    : "0" (val));

	asm("bswapq %0" : "=r" (val) : "0" (val));

	return val;

#endif

}

arch/x86/kernel/cpu/bugs.c

+2 −11
Original line number Diff line number Diff line
@@ -136,24 +136,15 @@ static void __init check_popad(void) 
/*

 * Check whether we are able to run this kernel safely on SMP.

 *

 * - In order to run on a i386, we need to be compiled for i386

 *   (for due to lack of "invlpg" and working WP on a i386)

 * - i386 is no longer supported.

 * - In order to run on anything without a TSC, we need to be

 *   compiled for a i486.

 */



static void __init check_config(void)

{

/*

 * We'd better not be a i386 if we're configured to use some

 * i486+ only features! (WP works in supervisor mode and the

 * new "invlpg" and "bswap" instructions)

 */

#if defined(CONFIG_X86_WP_WORKS_OK) || defined(CONFIG_X86_INVLPG) || \

	defined(CONFIG_X86_BSWAP)

	if (boot_cpu_data.x86 == 3)

	if (boot_cpu_data.x86 < 4)

		panic("Kernel requires i486+ for 'invlpg' and other features");

#endif

}