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Commit e5b28861 authored by Nicolin Chen's avatar Nicolin Chen Committed by Vinod Koul
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Revert "ARM: dts: imx: use dual-fifo sdma script for ssi"



This reverts commit b1d27c79.

Previously we switched the SSI scriprt to dual-fifo mode to reduce playback
underrun issue, which is only included by SDMA firmware version 2. However,
there are quite a lot people still using version 1 or default firmware in
the ROM code of SoC while these two kinds of firmwares do not support the
dual-fifo script and the audio function on their platform would be broken.

Thus this patch provisionally reverts the dual-fifo script to the original
single fifo script to meet all kinds of users' requirements, including the
version 1/2 or inner ROM firmware.

Reported-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: default avatarNicolin Chen <Guangyu.Chen@freescale.com>
Tested-by: default avatarFabio Estevam <fabio.estevam@freescale.com>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 6fb9063c
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+2 −2
Original line number Original line Diff line number Diff line
@@ -159,8 +159,8 @@
					reg = <0x70014000 0x4000>;
					reg = <0x70014000 0x4000>;
					interrupts = <30>;
					interrupts = <30>;
					clocks = <&clks 49>;
					clocks = <&clks 49>;
					dmas = <&sdma 24 22 0>,
					dmas = <&sdma 24 1 0>,
					       <&sdma 25 22 0>;
					       <&sdma 25 1 0>;
					dma-names = "rx", "tx";
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
+2 −2
Original line number Original line Diff line number Diff line
@@ -153,8 +153,8 @@
					reg = <0x50014000 0x4000>;
					reg = <0x50014000 0x4000>;
					interrupts = <30>;
					interrupts = <30>;
					clocks = <&clks 49>;
					clocks = <&clks 49>;
					dmas = <&sdma 24 22 0>,
					dmas = <&sdma 24 1 0>,
					       <&sdma 25 22 0>;
					       <&sdma 25 1 0>;
					dma-names = "rx", "tx";
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
					fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
+6 −6
Original line number Original line Diff line number Diff line
@@ -236,8 +236,8 @@
					reg = <0x02028000 0x4000>;
					reg = <0x02028000 0x4000>;
					interrupts = <0 46 0x04>;
					interrupts = <0 46 0x04>;
					clocks = <&clks 178>;
					clocks = <&clks 178>;
					dmas = <&sdma 37 22 0>,
					dmas = <&sdma 37 1 0>,
					       <&sdma 38 22 0>;
					       <&sdma 38 1 0>;
					dma-names = "rx", "tx";
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <38 37>;
					fsl,ssi-dma-events = <38 37>;
@@ -249,8 +249,8 @@
					reg = <0x0202c000 0x4000>;
					reg = <0x0202c000 0x4000>;
					interrupts = <0 47 0x04>;
					interrupts = <0 47 0x04>;
					clocks = <&clks 179>;
					clocks = <&clks 179>;
					dmas = <&sdma 41 22 0>,
					dmas = <&sdma 41 1 0>,
					       <&sdma 42 22 0>;
					       <&sdma 42 1 0>;
					dma-names = "rx", "tx";
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <42 41>;
					fsl,ssi-dma-events = <42 41>;
@@ -262,8 +262,8 @@
					reg = <0x02030000 0x4000>;
					reg = <0x02030000 0x4000>;
					interrupts = <0 48 0x04>;
					interrupts = <0 48 0x04>;
					clocks = <&clks 180>;
					clocks = <&clks 180>;
					dmas = <&sdma 45 22 0>,
					dmas = <&sdma 45 1 0>,
					       <&sdma 46 22 0>;
					       <&sdma 46 1 0>;
					dma-names = "rx", "tx";
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,fifo-depth = <15>;
					fsl,ssi-dma-events = <46 45>;
					fsl,ssi-dma-events = <46 45>;
+6 −6
Original line number Original line Diff line number Diff line
@@ -199,8 +199,8 @@
					reg = <0x02028000 0x4000>;
					reg = <0x02028000 0x4000>;
					interrupts = <0 46 0x04>;
					interrupts = <0 46 0x04>;
					clocks = <&clks IMX6SL_CLK_SSI1>;
					clocks = <&clks IMX6SL_CLK_SSI1>;
					dmas = <&sdma 37 22 0>,
					dmas = <&sdma 37 1 0>,
					       <&sdma 38 22 0>;
					       <&sdma 38 1 0>;
					dma-names = "rx", "tx";
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,fifo-depth = <15>;
					status = "disabled";
					status = "disabled";
@@ -211,8 +211,8 @@
					reg = <0x0202c000 0x4000>;
					reg = <0x0202c000 0x4000>;
					interrupts = <0 47 0x04>;
					interrupts = <0 47 0x04>;
					clocks = <&clks IMX6SL_CLK_SSI2>;
					clocks = <&clks IMX6SL_CLK_SSI2>;
					dmas = <&sdma 41 22 0>,
					dmas = <&sdma 41 1 0>,
					       <&sdma 42 22 0>;
					       <&sdma 42 1 0>;
					dma-names = "rx", "tx";
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,fifo-depth = <15>;
					status = "disabled";
					status = "disabled";
@@ -223,8 +223,8 @@
					reg = <0x02030000 0x4000>;
					reg = <0x02030000 0x4000>;
					interrupts = <0 48 0x04>;
					interrupts = <0 48 0x04>;
					clocks = <&clks IMX6SL_CLK_SSI3>;
					clocks = <&clks IMX6SL_CLK_SSI3>;
					dmas = <&sdma 45 22 0>,
					dmas = <&sdma 45 1 0>,
					       <&sdma 46 22 0>;
					       <&sdma 46 1 0>;
					dma-names = "rx", "tx";
					dma-names = "rx", "tx";
					fsl,fifo-depth = <15>;
					fsl,fifo-depth = <15>;
					status = "disabled";
					status = "disabled";