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Commit e53c0772 authored by Florian Fainelli's avatar Florian Fainelli Committed by Arnd Bergmann
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Documentation: devicetree: add Broadcom GISB arbiter bindings 



This patch adds the Broadcom GISB arbiter Device Tree binding that is
used on all Broadcom Set-top-box System-on-a-chip.

Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent 44127b77

Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt

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Broadcom GISB bus Arbiter controller



Required properties:



- compatible: should be "brcm,gisb-arb"

- reg: specifies the base physical address and size of the registers

- interrupt-parent: specifies the phandle to the parent interrupt controller

  this arbiter gets interrupt line from

- interrupts: specifies the two interrupts (timeout and TEA) to be used from

  the parent interrupt controller



Optional properties:



- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB

  masters are valid at the system level

- brcm,gisb-arb-master-names: string list of the litteral name of the GISB

  masters. Should match the number of bits set in brcm,gisb-master-mask and

  the order in which they appear



Example:



gisb-arb@f0400000 {

	compatible = "brcm,gisb-arb";

	reg = <0xf0400000 0x800>;

	interrupts = <0>, <2>;

	interrupt-parent = <&sun_l2_intc>;



	brcm,gisb-arb-master-mask = <0x7>;

	brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";

};