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Commit e522c846 authored by Graf Yang's avatar Graf Yang Committed by Mike Frysinger
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Blackfin: work around anomaly 05000287 



Make sure we work around anomaly 05000287 by configuring different port
preferences for the data cache.

Signed-off-by: default avatarGraf Yang <graf.yang@analog.com>
Signed-off-by: default avatarMike Frysinger <vapier@gentoo.org>
parent a9a59e30

arch/blackfin/kernel/cplb-mpu/cacheinit.c

+8 −1
Original line number Diff line number Diff line
@@ -55,7 +55,14 @@ void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl) 
	}



	ctrl = bfin_read_DMEM_CONTROL();

	ctrl |= DMEM_CNTR;



	/*

	 *  Anomaly notes:

	 *  05000287 - We implement workaround #2 - Change the DMEM_CONTROL

	 *  register, so that the port preferences for DAG0 and DAG1 are set

	 *  to port B

	 */

	ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);

	bfin_write_DMEM_CONTROL(ctrl);

	SSYNC();

}