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Commit e41f3207 authored by Linus Walleij's avatar Linus Walleij
Browse files

Merge tag 'sh-pfc-for-v4.12-tag3' of... 

Merge tag 'sh-pfc-for-v4.12-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.12 (take three)

  - Miscellaneous fixes for R-Car M2-W and R-Car E2.
parents 5e553521 5f4c8caf

drivers/pinctrl/sh-pfc/pfc-r8a7791.c

+11 −7
Original line number Diff line number Diff line
@@ -203,7 +203,7 @@ enum { 


	/* IPSR6 */

	FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,

	FN_SCIF_CLK, FN_BPFCLK_E,

	FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,

	FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,

	FN_SCIFA2_RXD, FN_FMIN_E,

	FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
@@ -573,7 +573,7 @@ enum { 


	/* IPSR6 */

	AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,

	SCIF_CLK_MARK, BPFCLK_E_MARK,

	SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,

	AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,

	SCIFA2_RXD_MARK, FMIN_E_MARK,

	AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
@@ -1010,14 +1010,17 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),

	PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),

	PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),

	PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),

	PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),

	PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),

	PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),

	PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),

	PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),

	PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),

	PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),

	PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),

	PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),

	PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),

	PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),

	PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),

	PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
@@ -1090,6 +1093,7 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),

	PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),

	PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),

	PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),

	PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),

	PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),

	PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
@@ -1099,7 +1103,7 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),

	PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),

	PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),

	PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),

	PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),

	PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),

	PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),

	PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
@@ -5707,7 +5711,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
	},

	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,

			     2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {

		/* IP2_31_20 [2] */

		/* IP2_31_30 [2] */

		0, 0, 0, 0,

		/* IP2_29_27 [3] */

		FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
@@ -5727,7 +5731,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP2_15_13 [3] */

		FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,

		0, 0, 0,

		/* IP2_12_0 [3] */

		/* IP2_12_10 [3] */

		FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,

		0, 0, 0,

		/* IP2_9_7 [3] */
@@ -5896,7 +5900,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0,

		/* IP6_2_0 [3] */

		FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,

		FN_SCIF_CLK, 0, FN_BPFCLK_E,

		FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,

		0, 0, }

	},

	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
@@ -6038,7 +6042,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		/* IP10_24_22 [3] */

		FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,

		0, 0, 0,

		/* IP10_21_29 [3] */

		/* IP10_21_19 [3] */

		FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,

		FN_TS_SDATA0_C, FN_ATACS11_N,

		0, 0, 0,

drivers/pinctrl/sh-pfc/pfc-r8a7794.c

+8 −8
Original line number Diff line number Diff line
@@ -281,8 +281,8 @@ enum { 
	FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,

	FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,

	FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,

	FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,

	FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B,

	FN_ATAWR0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,

	FN_MDATA, FN_ATAG0_N, FN_ETH_RXD1_B,



	/* IPSR13 */

	FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
@@ -575,8 +575,8 @@ enum { 
	ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,

	VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,

	SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,

	ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,

	VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK,

	ATAWR0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,

	VI1_DATA2_MARK, MDATA_MARK, ATAG0_N_MARK, ETH_RXD1_B_MARK,



	/* IPSR13 */

	SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
@@ -1413,13 +1413,13 @@ static const u16 pinmux_data[] = { 
	PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),

	PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),

	PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),

	PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N),

	PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),

	PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),

	PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),

	PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),

	PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),

	PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),

	PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N),

	PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),

	PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),



	/* IPSR13 */
@@ -4938,10 +4938,10 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { 
		0, 0, 0, 0,

		/* IP12_29_27 [3] */

		FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,

		FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0,

		FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,

		/* IP12_26_24 [3] */

		FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,

		FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0,

		FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,

		/* IP12_23_21 [3] */

		FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,

		FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,