Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e3f0a401 authored by Alexandre Belloni's avatar Alexandre Belloni Committed by Sebastian Reichel
Browse files

ARM: at91: define LPDDR types 



The Atmel MPDDR controller support LPDDR2 and LPDDR3 memories, add their
types.

Cc: <stable@vger.kernel.org> # 4.4+
Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: default avatarSebastian Reichel <sre@kernel.org>
parent 7ce7d89f

include/soc/at91/at91sam9_ddrsdr.h

+3 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ 
#define			AT91_DDRSDRC_LPCB_POWER_DOWN		2

#define			AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN	3

#define		AT91_DDRSDRC_CLKFR	(1 << 2)	/* Clock Frozen */

#define		AT91_DDRSDRC_LPDDR2_PWOFF	(1 << 3)	/* LPDDR Power Off */

#define		AT91_DDRSDRC_PASR	(7 << 4)	/* Partial Array Self Refresh */

#define		AT91_DDRSDRC_TCSR	(3 << 8)	/* Temperature Compensated Self Refresh */

#define		AT91_DDRSDRC_DS		(3 << 10)	/* Drive Strength */
@@ -96,7 +97,9 @@ 
#define			AT91_DDRSDRC_MD_SDR		0

#define			AT91_DDRSDRC_MD_LOW_POWER_SDR	1

#define			AT91_DDRSDRC_MD_LOW_POWER_DDR	3

#define			AT91_DDRSDRC_MD_LPDDR3		5

#define			AT91_DDRSDRC_MD_DDR2		6	/* [SAM9 Only] */

#define			AT91_DDRSDRC_MD_LPDDR2		7

#define		AT91_DDRSDRC_DBW	(1 << 4)		/* Data Bus Width */

#define			AT91_DDRSDRC_DBW_32BITS		(0 <<  4)

#define			AT91_DDRSDRC_DBW_16BITS		(1 <<  4)