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Unverified Commit e3b74202 authored by Viresh Kumar's avatar Viresh Kumar Committed by Maxime Ripard
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ARM: dts: sunxi: Add missing cooling device properties for CPUs 



The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Fix other missing properties (clocks, OPP, clock latency) as well to
make it all work.

Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent ce397d21

arch/arm/boot/dts/sun6i-a31.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -119,18 +119,48 @@ 
			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

			#cooling-cells = <2>;

		};



		cpu@2 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <2>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

			#cooling-cells = <2>;

		};



		cpu@3 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <3>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

			#cooling-cells = <2>;

		};

	};

arch/arm/boot/dts/sun7i-a20.dtsi

+13 −0
Original line number Diff line number Diff line
@@ -122,6 +122,19 @@ 
			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <1>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

				/* kHz	  uV */

				960000	1400000

				912000	1400000

				864000	1300000

				720000	1200000

				528000	1100000

				312000	1000000

				144000	1000000

				>;

			#cooling-cells = <2>;

		};

	};

arch/arm/boot/dts/sun8i-a33.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -132,21 +132,30 @@ 
		};



		cpu@1 {

			clocks = <&ccu CLK_CPUX>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu0_opp_table>;

			#cooling-cells = <2>;

		};



		cpu@2 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <2>;

			clocks = <&ccu CLK_CPUX>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu0_opp_table>;

			#cooling-cells = <2>;

		};



		cpu@3 {

			compatible = "arm,cortex-a7";

			device_type = "cpu";

			reg = <3>;

			clocks = <&ccu CLK_CPUX>;

			clock-names = "cpu";

			operating-points-v2 = <&cpu0_opp_table>;

			#cooling-cells = <2>;

		};

	};