Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued

Rudolf Marek <R.Marek@sh.cvut.cz>

Rui Saraiva <rmps@joel.ist.utl.pt>

Sachin P Sant <ssant@in.ibm.com>

Sarangdhar Joshi <spjoshi@codeaurora.org>

Sam Ravnborg <sam@mars.ravnborg.org>

Santosh Shilimkar <ssantosh@kernel.org>

Santosh Shilimkar <santosh.shilimkar@oracle.org>

Simon Kelley <simon@thekelleys.org.uk>

Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>

Stephen Hemminger <shemminger@osdl.org>

Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>

Subhash Jadavani <subhashj@codeaurora.org>

Sudeep Holla <sudeep.holla@arm.com> Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>

Sumit Semwal <sumit.semwal@ti.com>

Tejun Heo <htejun@gmail.com>

Thomas Graf <tgraf@suug.ch>

Thomas Pedersen <twp@codeaurora.org>

Tony Luck <tony.luck@intel.com>

Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>

Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>

What:		/sys/devices/.../deferred_probe

Date:		August 2016

Contact:	Ben Hutchings <ben.hutchings@codethink.co.uk>

Description:

		The /sys/devices/.../deferred_probe attribute is

		present for all devices.  If a driver detects during

		probing a device that a related device is not yet

		ready, it may defer probing of the first device.  The

		kernel will retry probing the first device after any

		other device is successfully probed.  This attribute

		reads as 1 if probing of this device is currently

		deferred, or 0 otherwise.

- adi,input-justification: The input bit justification ("left", "evenly",

  "right").

- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.

- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.

- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip.

- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V

  on the chip.

- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is

  needed only for ADV7511.

The following properties are required for ADV7533:

- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should

  be one of 1, 2, 3 or 4.

- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip.

- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip.

- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be

  either 1.2V or 1.8V.

Optional properties:

DesignWare HDMI bridge bindings

Required properties:

- compatible: platform specific such as:

   * "snps,dw-hdmi-tx"

   * "fsl,imx6q-hdmi"

   * "fsl,imx6dl-hdmi"

   * "rockchip,rk3288-dw-hdmi"

- reg: Physical base address and length of the controller's registers.

- interrupts: The HDMI interrupt number

- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,

  as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,

  the clocks are soc specific, the clock-names should be "iahb", "isfr"

-port@[X]: SoC specific port nodes with endpoint definitions as defined

   in Documentation/devicetree/bindings/media/video-interfaces.txt,

   please refer to the SoC specific binding document:

    * Documentation/devicetree/bindings/display/imx/hdmi.txt

    * Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt

Optional properties

- reg-io-width: the width of the reg:1,4, default set to 1 if not present

- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,

  if the property is omitted, a functionally reduced I2C bus

  controller on DW HDMI is probed

- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"

Example:

	hdmi: hdmi@0120000 {

		compatible = "fsl,imx6q-hdmi";

		reg = <0x00120000 0x9000>;

		interrupts = <0 115 0x04>;

		gpr = <&gpr>;

		clocks = <&clks 123>, <&clks 124>;

		clock-names = "iahb", "isfr";

		ddc-i2c-bus = <&i2c2>;

		port@0 {

			reg = <0>;

			hdmi_mux_0: endpoint {

				remote-endpoint = <&ipu1_di0_hdmi>;

			};

		};

		port@1 {

			reg = <1>;

			hdmi_mux_1: endpoint {

				remote-endpoint = <&ipu1_di1_hdmi>;

			};

		};

	};

Synopsys DesignWare HDMI TX Encoder

===================================

This document defines device tree properties for the Synopsys DesignWare HDMI

TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding

specification by itself but is meant to be referenced by platform-specific

device tree bindings.

When referenced from platform device tree bindings the properties defined in

this document are defined as follows. The platform device tree bindings are

responsible for defining whether each property is required or optional.

- reg: Memory mapped base address and length of the DWC HDMI TX registers.

- reg-io-width: Width of the registers specified by the reg property. The

  value is expressed in bytes and must be equal to 1 or 4 if specified. The

  register width defaults to 1 if the property is not present.

- interrupts: Reference to the DWC HDMI TX interrupt.

- clocks: References to all the clocks specified in the clock-names property

  as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.

- clock-names: The DWC HDMI TX uses the following clocks.

  - "iahb" is the bus clock for either AHB and APB (mandatory).

  - "isfr" is the internal register configuration clock (mandatory).

  - "cec" is the HDMI CEC controller main clock (optional).

- ports: The connectivity of the DWC HDMI TX with the rest of the system is

  expressed in using ports as specified in the device graph bindings defined

  in Documentation/devicetree/bindings/graph.txt. The numbering of the ports

  is platform-specific.

Device-Tree bindings for HDMI Transmitter

Freescale i.MX6 DWC HDMI TX Encoder

===================================

HDMI Transmitter

================

The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP

with a companion PHY IP.

These DT bindings follow the Synopsys DWC HDMI TX bindings defined in

Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the

following device-specific properties.

The HDMI Transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP

with accompanying PHY IP.

Required properties:

 - #address-cells : should be <1>

 - #size-cells : should be <0>

 - compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".

 - gpr : should be <&gpr>.

   The phandle points to the iomuxc-gpr region containing the HDMI

- compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".

- reg: See dw_hdmi.txt.

- interrupts: HDMI interrupt number

- clocks: See dw_hdmi.txt.

- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.

- ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,

  numbered 0 to 3, corresponding to the four inputs of the HDMI multiplexer.

  Each port shall have a single endpoint.

- gpr : Shall contain a phandle to the iomuxc-gpr region containing the HDMI

  multiplexer control register.

 - clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described

   in Documentation/devicetree/bindings/clock/clock-bindings.txt and

   Documentation/devicetree/bindings/clock/imx6q-clock.txt.

 - port@[0-4]: Up to four port nodes with endpoint definitions as defined in

   Documentation/devicetree/bindings/media/video-interfaces.txt,

   corresponding to the four inputs to the HDMI multiplexer.

Optional properties:

 - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing

Optional properties

- ddc-i2c-bus: The HDMI DDC bus can be connected to either a system I2C master

  or the functionally-reduced I2C master contained in the DWC HDMI. When

  connected to a system I2C master this property contains a phandle to that

  I2C master controller.

example:

Example:

	gpr: iomuxc-gpr@020e0000 {

		/* ... */