Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e2724e9d authored by Jeremy Compostella's avatar Jeremy Compostella Committed by Thomas Gleixner
Browse files

x86/tsc: Add missing Cherrytrail frequency to the table 



Intel Cherrytrail is based on Airmont core so MSR_FSB_FREQ[2:0] = 4
means that the CPU reference clock runs at 80MHz.  Add this missing
frequency to the table.

Signed-off-by: default avatarJeremy Compostella <jeremy.compostella@intel.com>
Link: http://lkml.kernel.org/r/87y47gty89.fsf@intel.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 9a7a076e

arch/x86/kernel/tsc_msr.c

+3 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ 
#include <asm/param.h>



/* CPU reference clock frequency: in KHz */

#define FREQ_80		80000

#define FREQ_83		83200

#define FREQ_100	99840

#define FREQ_133	133200
@@ -56,6 +57,8 @@ static struct freq_desc freq_desc_tables[] = { 
	{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },

	/* ANN */

	{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },

	/* AIRMONT */

	{ 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80,	0, 0, 0 } },

};



static int match_cpu(u8 family, u8 model)