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Commit e2560b10 authored by Nicholas Piggin's avatar Nicholas Piggin Committed by Paul Mackerras
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KVM: PPC: Book3S HV: Make radix use correct tlbie sequence in kvmppc_radix_tlbie_page 



The standard eieio ; tlbsync ; ptesync must follow tlbie to ensure it
is ordered with respect to subsequent operations.

Signed-off-by: default avatarNicholas Piggin <npiggin@gmail.com>
Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
parent 57b8daa7

arch/powerpc/kvm/book3s_64_mmu_radix.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -162,7 +162,7 @@ static void kvmppc_radix_tlbie_page(struct kvm *kvm, unsigned long addr, 
	if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG))

	if (cpu_has_feature(CPU_FTR_P9_TLBIE_BUG))

		asm volatile(PPC_TLBIE_5(%0, %1, 0, 0, 1)

		asm volatile(PPC_TLBIE_5(%0, %1, 0, 0, 1)

			     : : "r" (addr), "r" (kvm->arch.lpid) : "memory");

			     : : "r" (addr), "r" (kvm->arch.lpid) : "memory");

	asm volatile("ptesync": : :"memory");

	asm volatile("eieio ; tlbsync ; ptesync": : :"memory");

}

}





static void kvmppc_radix_flush_pwc(struct kvm *kvm, unsigned long addr)

static void kvmppc_radix_flush_pwc(struct kvm *kvm, unsigned long addr)
@@ -173,7 +173,7 @@ static void kvmppc_radix_flush_pwc(struct kvm *kvm, unsigned long addr) 
	/* RIC=1 PRS=0 R=1 IS=2 */

	/* RIC=1 PRS=0 R=1 IS=2 */

	asm volatile(PPC_TLBIE_5(%0, %1, 1, 0, 1)

	asm volatile(PPC_TLBIE_5(%0, %1, 1, 0, 1)

		     : : "r" (rb), "r" (kvm->arch.lpid) : "memory");

		     : : "r" (rb), "r" (kvm->arch.lpid) : "memory");

	asm volatile("ptesync": : :"memory");

	asm volatile("eieio ; tlbsync ; ptesync": : :"memory");

}

}





unsigned long kvmppc_radix_update_pte(struct kvm *kvm, pte_t *ptep,

unsigned long kvmppc_radix_update_pte(struct kvm *kvm, pte_t *ptep,