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Commit e1fdc473 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: remove wait_for_vblank argument form intel_enable_pipe 



Add a nice comment explaining why we shouldn't wait for a vblank on
all cases, wait based on the HW gen, and add a comment saying we
should probably skip that wait on some of the previous HW gens.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent fbf3218a

drivers/gpu/drm/i915/intel_display.c

+14 −7
Original line number Diff line number Diff line
@@ -1747,12 +1747,11 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) 
/**

 * intel_enable_pipe - enable a pipe, asserting requirements

 * @crtc: crtc responsible for the pipe

 * @wait_for_vblank: whether we should for a vblank or not after enabling it

 *

 * Enable @crtc's pipe, making sure that various hardware specific requirements

 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.

 */

static void intel_enable_pipe(struct intel_crtc *crtc, bool wait_for_vblank)

static void intel_enable_pipe(struct intel_crtc *crtc)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1799,7 +1798,15 @@ static void intel_enable_pipe(struct intel_crtc *crtc, bool wait_for_vblank) 


	I915_WRITE(reg, val | PIPECONF_ENABLE);

	POSTING_READ(reg);

	if (wait_for_vblank)



	/*

	 * There's no guarantee the pipe will really start running now. It

	 * depends on the Gen, the output type and the relative order between

	 * pipe and plane enabling. Avoid waiting on HSW+ since it's not

	 * necessary.

	 * TODO: audit the previous gens.

	 */

	if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))

		intel_wait_for_vblank(dev_priv->dev, pipe);

}
@@ -3596,7 +3603,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) 
	intel_crtc_load_lut(crtc);



	intel_update_watermarks(crtc);

	intel_enable_pipe(intel_crtc, true);

	intel_enable_pipe(intel_crtc);

	intel_enable_primary_plane(dev_priv, plane, pipe);

	intel_enable_planes(crtc);

	intel_crtc_update_cursor(crtc, true);
@@ -3741,7 +3748,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) 
	intel_ddi_enable_transcoder_func(crtc);



	intel_update_watermarks(crtc);

	intel_enable_pipe(intel_crtc, false);

	intel_enable_pipe(intel_crtc);



	if (intel_crtc->config.has_pch_encoder)

		lpt_pch_enable(crtc);
@@ -4166,7 +4173,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) 
	intel_crtc_load_lut(crtc);



	intel_update_watermarks(crtc);

	intel_enable_pipe(intel_crtc, true);

	intel_enable_pipe(intel_crtc);

	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);

	intel_enable_primary_plane(dev_priv, plane, pipe);

	intel_enable_planes(crtc);
@@ -4205,7 +4212,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) 
	intel_crtc_load_lut(crtc);



	intel_update_watermarks(crtc);

	intel_enable_pipe(intel_crtc, true);

	intel_enable_pipe(intel_crtc);

	intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);

	intel_enable_primary_plane(dev_priv, plane, pipe);

	intel_enable_planes(crtc);