nds32: Assembly macros and definitions

// SPDX-License-Identifier: GPL-2.0

// Copyright (C) 2005-2017 Andes Technology Corporation

#ifndef __NDS32_ASSEMBLER_H__

#define __NDS32_ASSEMBLER_H__

.macro gie_disable

	setgie.d

	dsb

.endm

.macro gie_enable

	setgie.e

	dsb

.endm

.macro gie_save oldpsw

	mfsr \oldpsw, $ir0

	setgie.d

        dsb

.endm

.macro gie_restore oldpsw

	andi \oldpsw, \oldpsw, #0x1

	beqz \oldpsw, 7001f

	setgie.e

	dsb

7001:

.endm

#define USER(insn,  reg, addr, opr)	\

9999:	insn  reg, addr, opr;		\

	.section __ex_table,"a";	\

	.align 3;			\

	.long	9999b, 9001f;		\

	.previous

#endif /* __NDS32_ASSEMBLER_H__ */

// SPDX-License-Identifier: GPL-2.0

// Copyright (C) 2005-2017 Andes Technology Corporation

#ifndef _ASM_NDS32_NDS32_H_

#define _ASM_NDS32_NDS32_H_

#include <asm/bitfield.h>

#include <asm/cachectl.h>

#ifndef __ASSEMBLY__

#include <linux/init.h>

#include <asm/barrier.h>

#include <nds32_intrinsic.h>

#ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE

#define FP_OFFSET (-3)

#else

#define FP_OFFSET (-2)

#endif

extern void __init early_trap_init(void);

static inline void GIE_ENABLE(void)

{

	mb();

	__nds32__gie_en();

}

static inline void GIE_DISABLE(void)

{

	mb();

	__nds32__gie_dis();

}

static inline unsigned long CACHE_SET(unsigned char cache)

{

	if (cache == ICACHE)

		return 64 << ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISET) >>

			      ICM_CFG_offISET);

	else

		return 64 << ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSET) >>

			      DCM_CFG_offDSET);

}

static inline unsigned long CACHE_WAY(unsigned char cache)

{

	if (cache == ICACHE)

		return 1 +

		    ((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskIWAY) >> ICM_CFG_offIWAY);

	else

		return 1 +

		    ((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDWAY) >> DCM_CFG_offDWAY);

}

static inline unsigned long CACHE_LINE_SIZE(unsigned char cache)

{

	if (cache == ICACHE)

		return 8 <<

		    (((__nds32__mfsr(NDS32_SR_ICM_CFG) & ICM_CFG_mskISZ) >> ICM_CFG_offISZ) - 1);

	else

		return 8 <<

		    (((__nds32__mfsr(NDS32_SR_DCM_CFG) & DCM_CFG_mskDSZ) >> DCM_CFG_offDSZ) - 1);

}

#endif /* __ASSEMBLY__ */

#define IVB_BASE		PHYS_OFFSET	/* in user space for intr/exc/trap/break table base, 64KB aligned

						 * We defined at the start of the physical memory */

/* dispatched sub-entry exception handler numbering */

#define RD_PROT			0	/* read protrection */

#define WRT_PROT		1	/* write protection */

#define NOEXEC			2	/* non executable */

#define PAGE_MODIFY		3	/* page modified */

#define ACC_BIT			4	/* access bit */

#define RESVED_PTE		5	/* reserved PTE attribute */

/* reserved 6 ~ 16 */

#endif /* _ASM_NDS32_NDS32_H_ */

// SPDX-License-Identifier: GPL-2.0

// Copyright (C) 2005-2017 Andes Technology Corporation

#include <linux/sched.h>

#include <linux/sched/task_stack.h>

#include <linux/kbuild.h>

#include <asm/thread_info.h>

#include <asm/ptrace.h>

int main(void)

{

	DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags));

	DEFINE(TSK_TI_PREEMPT,

	       offsetof(struct task_struct, thread_info.preempt_count));

	DEFINE(THREAD_CPU_CONTEXT,

	       offsetof(struct task_struct, thread.cpu_context));

	DEFINE(OSP_OFFSET, offsetof(struct pt_regs, osp));

	DEFINE(SP_OFFSET, offsetof(struct pt_regs, sp));

	DEFINE(FUCOP_CTL_OFFSET, offsetof(struct pt_regs, fucop_ctl));

	DEFINE(IPSW_OFFSET, offsetof(struct pt_regs, ipsw));

	DEFINE(SYSCALLNO_OFFSET, offsetof(struct pt_regs, syscallno));

	DEFINE(IPC_OFFSET, offsetof(struct pt_regs, ipc));

	DEFINE(R0_OFFSET, offsetof(struct pt_regs, uregs[0]));

	DEFINE(R15_OFFSET, offsetof(struct pt_regs, uregs[15]));

	DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);

	DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);

	return 0;

}