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Commit e1b43e3f authored by Borislav Petkov's avatar Borislav Petkov
Browse files

x86, microcode: Share native MSR accessing variants 



We want to use those in AMD's early loading path too. Also, add a
native_wrmsrl variant.

Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Tested-by: default avatarAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
parent 5aa3d718

arch/x86/include/asm/microcode.h

+15 −0
Original line number Diff line number Diff line 
#ifndef _ASM_X86_MICROCODE_H

#define _ASM_X86_MICROCODE_H



#define native_rdmsr(msr, val1, val2)			\

do {							\

	u64 __val = native_read_msr((msr));		\

	(void)((val1) = (u32)__val);			\

	(void)((val2) = (u32)(__val >> 32));		\

} while (0)



#define native_wrmsr(msr, low, high)			\

	native_write_msr(msr, low, high)



#define native_wrmsrl(msr, val)				\

	native_write_msr((msr),				\

			 (u32)((u64)(val)),		\

			 (u32)((u64)(val) >> 32))



struct cpu_signature {

	unsigned int sig;

	unsigned int pf;

arch/x86/kernel/microcode_intel_early.c

+0 −10
Original line number Diff line number Diff line
@@ -365,16 +365,6 @@ get_matching_model_microcode(int cpu, unsigned long start, 
	return state;

}



#define native_rdmsr(msr, val1, val2)		\

do {						\

	u64 __val = native_read_msr((msr));	\

	(void)((val1) = (u32)__val);		\

	(void)((val2) = (u32)(__val >> 32));	\

} while (0)



#define native_wrmsr(msr, low, high)		\

	native_write_msr(msr, low, high);



static int collect_cpu_info_early(struct ucode_cpu_info *uci)

{

	unsigned int val[2];