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Commit e164835a authored by Maruthi Srinivas Bayyavarapu's avatar Maruthi Srinivas Bayyavarapu Committed by Mark Brown
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ASoC: dwc: add quirk for different register offset 



DWC in ACP 2.x IP has different offsets for I2S_COMP_PARAM_* registers.
Added a quirk to support the same.

Signed-off-by: default avatarMaruthi Bayyavarapu <maruthi.bayyavarapu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent f4830312

include/sound/designware_i2s.h

+5 −0
Original line number Original line Diff line number Diff line
@@ -45,6 +45,11 @@ struct i2s_platform_data { 
	u32 snd_fmts;

	u32 snd_fmts;

	u32 snd_rates;

	u32 snd_rates;





	#define DW_I2S_QUIRK_COMP_REG_OFFSET	(1 << 0)

	unsigned int quirks;

	unsigned int i2s_reg_comp1;

	unsigned int i2s_reg_comp2;



	void *play_dma_data;

	void *play_dma_data;

	void *capture_dma_data;

	void *capture_dma_data;

	bool (*filter)(struct dma_chan *chan, void *slave);

	bool (*filter)(struct dma_chan *chan, void *slave);

sound/soc/dwc/designware_i2s.c

+14 −3
Original line number Original line Diff line number Diff line
@@ -94,6 +94,9 @@ struct dw_i2s_dev { 
	struct clk *clk;

	struct clk *clk;

	int active;

	int active;

	unsigned int capability;

	unsigned int capability;

	unsigned int quirks;

	unsigned int i2s_reg_comp1;

	unsigned int i2s_reg_comp2;

	struct device *dev;

	struct device *dev;





	/* data related to DMA transfers b/w i2s and DMAC */

	/* data related to DMA transfers b/w i2s and DMAC */
@@ -477,8 +480,8 @@ static int dw_configure_dai(struct dw_i2s_dev *dev, 
	 * Read component parameter registers to extract

	 * Read component parameter registers to extract

	 * the I2S block's configuration.

	 * the I2S block's configuration.

	 */

	 */

	u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);

	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);

	u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);

	u32 comp2 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp2);

	u32 idx;

	u32 idx;





	if (COMP1_TX_ENABLED(comp1)) {

	if (COMP1_TX_ENABLED(comp1)) {
@@ -521,7 +524,7 @@ static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev, 
				   struct resource *res,

				   struct resource *res,

				   const struct i2s_platform_data *pdata)

				   const struct i2s_platform_data *pdata)

{

{

	u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);

	u32 comp1 = i2s_read_reg(dev->i2s_base, dev->i2s_reg_comp1);

	u32 idx = COMP1_APB_DATA_WIDTH(comp1);

	u32 idx = COMP1_APB_DATA_WIDTH(comp1);

	int ret;

	int ret;
@@ -625,6 +628,14 @@ static int dw_i2s_probe(struct platform_device *pdev) 
	if (pdata) {

	if (pdata) {

		dev->capability = pdata->cap;

		dev->capability = pdata->cap;

		clk_id = NULL;

		clk_id = NULL;

		dev->quirks = pdata->quirks;

		if (dev->quirks & DW_I2S_QUIRK_COMP_REG_OFFSET) {

			dev->i2s_reg_comp1 = pdata->i2s_reg_comp1;

			dev->i2s_reg_comp2 = pdata->i2s_reg_comp2;

		} else {

			dev->i2s_reg_comp1 = I2S_COMP_PARAM_1;

			dev->i2s_reg_comp2 = I2S_COMP_PARAM_2;

		}

		ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);

		ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);

	} else {

	} else {

		clk_id = "i2sclk";

		clk_id = "i2sclk";