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Commit e10fa551 authored by Joonas Lahtinen's avatar Joonas Lahtinen
Browse files

drm/i915: Clean up PCI config register handling 



Do not use magic numbers, do not prefix stuff with "PCI_", do not
declare registers in implementation files. Also move the PCI
registers under correct comment in i915_reg.h.

v2:
- Consistently use BSM (not BDSM or other variants from PRM) (Chris)
- Also include register address to help identify the register (Chris)
v3:
- Refer to register value as *_val instead of *_reg (Chris)
v4:
- Make style checker happy

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
parent 44a71024

drivers/gpu/drm/i915/i915_dma.c

+16 −16
Original line number Diff line number Diff line
@@ -257,13 +257,6 @@ static int i915_get_bridge_dev(struct drm_device *dev) 
	return 0;

}



#define MCHBAR_I915 0x44

#define MCHBAR_I965 0x48

#define MCHBAR_SIZE (4*4096)



#define DEVEN_REG 0x54

#define   DEVEN_MCHBAR_EN (1 << 28)



/* Allocate space for the MCH regs if needed, return nonzero on error */

static int

intel_alloc_mchbar_resource(struct drm_device *dev)
@@ -325,7 +318,7 @@ intel_setup_mchbar(struct drm_device *dev) 
	dev_priv->mchbar_need_disable = false;



	if (IS_I915G(dev) || IS_I915GM(dev)) {

		pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);

		pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);

		enabled = !!(temp & DEVEN_MCHBAR_EN);

	} else {

		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
@@ -343,7 +336,7 @@ intel_setup_mchbar(struct drm_device *dev) 


	/* Space is allocated or reserved, so enable it. */

	if (IS_I915G(dev) || IS_I915GM(dev)) {

		pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,

		pci_write_config_dword(dev_priv->bridge_dev, DEVEN,

				       temp | DEVEN_MCHBAR_EN);

	} else {

		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
@@ -356,17 +349,24 @@ intel_teardown_mchbar(struct drm_device *dev) 
{

	struct drm_i915_private *dev_priv = dev->dev_private;

	int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;

	u32 temp;



	if (dev_priv->mchbar_need_disable) {

		if (IS_I915G(dev) || IS_I915GM(dev)) {

			pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);

			temp &= ~DEVEN_MCHBAR_EN;

			pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);

			u32 deven_val;



			pci_read_config_dword(dev_priv->bridge_dev, DEVEN,

					      &deven_val);

			deven_val &= ~DEVEN_MCHBAR_EN;

			pci_write_config_dword(dev_priv->bridge_dev, DEVEN,

					       deven_val);

		} else {

			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);

			temp &= ~1;

			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);

			u32 mchbar_val;



			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,

					      &mchbar_val);

			mchbar_val &= ~1;

			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,

					       mchbar_val);

		}

	}

drivers/gpu/drm/i915/i915_gem_stolen.c

+8 −6
Original line number Diff line number Diff line
@@ -95,9 +95,9 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) 
	u32 base;



	/* Almost universally we can find the Graphics Base of Stolen Memory

	 * at offset 0x5c in the igfx configuration space. On a few (desktop)

	 * machines this is also mirrored in the bridge device at different

	 * locations, or in the MCHBAR.

	 * at register BSM (0x5c) in the igfx configuration space. On a few

	 * (desktop) machines this is also mirrored in the bridge device at

	 * different locations, or in the MCHBAR.

	 *

	 * On 865 we just check the TOUD register.

	 *
@@ -107,9 +107,11 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev) 
	 */

	base = 0;

	if (INTEL_INFO(dev)->gen >= 3) {

		/* Read Graphics Base of Stolen Memory directly */

		pci_read_config_dword(dev->pdev, 0x5c, &base);

		base &= ~((1<<20) - 1);

		u32 bsm;



		pci_read_config_dword(dev->pdev, BSM, &bsm);



		base = bsm & BSM_MASK;

	} else if (IS_I865G(dev)) {

		u16 toud = 0;

drivers/gpu/drm/i915/i915_reg.h

+28 −10
Original line number Diff line number Diff line
@@ -79,6 +79,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 


/* PCI config space */



#define MCHBAR_I915 0x44

#define MCHBAR_I965 0x48

#define MCHBAR_SIZE (4 * 4096)



#define DEVEN 0x54

#define   DEVEN_MCHBAR_EN (1 << 28)



#define BSM 0x5c

#define   BSM_MASK (0xFFFF << 20)



#define HPLLCC	0xc0 /* 85x only */

#define   GC_CLOCK_CONTROL_MASK		(0x7 << 0)

#define   GC_CLOCK_133_200		(0 << 0)
@@ -90,6 +100,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   GC_CLOCK_166_266		(6 << 0)

#define   GC_CLOCK_166_250		(7 << 0)



#define I915_GDRST 0xc0 /* PCI config register */

#define   GRDOM_FULL		(0 << 2)

#define   GRDOM_RENDER		(1 << 2)

#define   GRDOM_MEDIA		(3 << 2)

#define   GRDOM_MASK		(3 << 2)

#define   GRDOM_RESET_STATUS	(1 << 1)

#define   GRDOM_RESET_ENABLE	(1 << 0)



#define GCDGMBUS 0xcc



#define GCFGC2	0xda

#define GCFGC	0xf0 /* 915+ only */

#define   GC_LOW_FREQUENCY_ENABLE	(1 << 7)
@@ -121,18 +141,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   I915_GC_RENDER_CLOCK_166_MHZ	(0 << 0)

#define   I915_GC_RENDER_CLOCK_200_MHZ	(1 << 0)

#define   I915_GC_RENDER_CLOCK_333_MHZ	(4 << 0)

#define GCDGMBUS 0xcc

#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */



#define ASLE	0xe4

#define ASLS	0xfc



#define SWSCI	0xe8

#define   SWSCI_SCISEL	(1 << 15)

#define   SWSCI_GSSCIE	(1 << 0)



#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */



/* Graphics reset regs */

#define I915_GDRST 0xc0 /* PCI config register */

#define  GRDOM_FULL	(0<<2)

#define  GRDOM_RENDER	(1<<2)

#define  GRDOM_MEDIA	(3<<2)

#define  GRDOM_MASK	(3<<2)

#define  GRDOM_RESET_STATUS (1<<1)

#define  GRDOM_RESET_ENABLE (1<<0)



#define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)

#define  ILK_GRDOM_FULL		(0<<1)

drivers/gpu/drm/i915/intel_opregion.c

+9 −15
Original line number Diff line number Diff line
@@ -34,12 +34,6 @@ 
#include "i915_drv.h"

#include "intel_drv.h"



#define PCI_ASLE		0xe4

#define PCI_ASLS		0xfc

#define PCI_SWSCI		0xe8

#define PCI_SWSCI_SCISEL	(1 << 15)

#define PCI_SWSCI_GSSCIE	(1 << 0)



#define OPREGION_HEADER_OFFSET 0

#define OPREGION_ACPI_OFFSET   0x100

#define   ACPI_CLID 0x01ac /* current lid state indicator */
@@ -251,7 +245,7 @@ static int swsci(struct drm_device *dev, u32 function, u32 parm, u32 *parm_out) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	struct opregion_swsci *swsci = dev_priv->opregion.swsci;

	u32 main_function, sub_function, scic;

	u16 pci_swsci;

	u16 swsci_val;

	u32 dslp;



	if (!swsci)
@@ -299,16 +293,16 @@ static int swsci(struct drm_device *dev, u32 function, u32 parm, u32 *parm_out) 
	swsci->scic = scic;



	/* Ensure SCI event is selected and event trigger is cleared. */

	pci_read_config_word(dev->pdev, PCI_SWSCI, &pci_swsci);

	if (!(pci_swsci & PCI_SWSCI_SCISEL) || (pci_swsci & PCI_SWSCI_GSSCIE)) {

		pci_swsci |= PCI_SWSCI_SCISEL;

		pci_swsci &= ~PCI_SWSCI_GSSCIE;

		pci_write_config_word(dev->pdev, PCI_SWSCI, pci_swsci);

	pci_read_config_word(dev->pdev, SWSCI, &swsci_val);

	if (!(swsci_val & SWSCI_SCISEL) || (swsci_val & SWSCI_GSSCIE)) {

		swsci_val |= SWSCI_SCISEL;

		swsci_val &= ~SWSCI_GSSCIE;

		pci_write_config_word(dev->pdev, SWSCI, swsci_val);

	}



	/* Use event trigger to tell bios to check the mail. */

	pci_swsci |= PCI_SWSCI_GSSCIE;

	pci_write_config_word(dev->pdev, PCI_SWSCI, pci_swsci);

	swsci_val |= SWSCI_GSSCIE;

	pci_write_config_word(dev->pdev, SWSCI, swsci_val);



	/* Poll for the result. */

#define C (((scic = swsci->scic) & SWSCI_SCIC_INDICATOR) == 0)
@@ -939,7 +933,7 @@ int intel_opregion_setup(struct drm_device *dev) 
	BUILD_BUG_ON(sizeof(struct opregion_asle) != 0x100);

	BUILD_BUG_ON(sizeof(struct opregion_asle_ext) != 0x400);



	pci_read_config_dword(dev->pdev, PCI_ASLS, &asls);

	pci_read_config_dword(dev->pdev, ASLS, &asls);

	DRM_DEBUG_DRIVER("graphic opregion physical addr: 0x%x\n", asls);

	if (asls == 0) {

		DRM_DEBUG_DRIVER("ACPI OpRegion not supported!\n");

drivers/gpu/drm/i915/intel_panel.c

+2 −2
Original line number Diff line number Diff line
@@ -504,7 +504,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector) 
	if (panel->backlight.combination_mode) {

		u8 lbpc;



		pci_read_config_byte(dev_priv->dev->pdev, PCI_LBPC, &lbpc);

		pci_read_config_byte(dev_priv->dev->pdev, LBPC, &lbpc);

		val *= lbpc;

	}
@@ -592,7 +592,7 @@ static void i9xx_set_backlight(struct intel_connector *connector, u32 level) 


		lbpc = level * 0xfe / panel->backlight.max + 1;

		level /= lbpc;

		pci_write_config_byte(dev_priv->dev->pdev, PCI_LBPC, lbpc);

		pci_write_config_byte(dev_priv->dev->pdev, LBPC, lbpc);

	}



	if (IS_GEN4(dev_priv)) {