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Commit e0908085 authored by Rex Feany's avatar Rex Feany Committed by Benjamin Herrenschmidt
Browse files

powerpc/8xx: Fix regression introduced by cache coherency rewrite 



After upgrading to the latest kernel on my mpc875 userspace started
running incredibly slow (hours to get to a shell, even!).
I tracked it down to commit 8d30c14c,
that patch removed a work-around for the 8xx. Adding it
back makes my problem go away.

Signed-off-by: default avatarRex Feany <rfeany@mrv.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
parent daf8f403

arch/powerpc/mm/pgtable.c

+16 −3
Original line number Original line Diff line number Diff line
@@ -30,6 +30,8 @@ 
#include <asm/tlbflush.h>

#include <asm/tlbflush.h>

#include <asm/tlb.h>

#include <asm/tlb.h>





#include "mmu_decl.h"



DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);

DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);





#ifdef CONFIG_SMP

#ifdef CONFIG_SMP
@@ -166,7 +168,7 @@ struct page * maybe_pte_to_page(pte_t pte) 
 * support falls into the same category.

 * support falls into the same category.

 */

 */





static pte_t set_pte_filter(pte_t pte)

static pte_t set_pte_filter(pte_t pte, unsigned long addr)

{

{

	pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);

	pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);

	if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||

	if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
@@ -175,6 +177,17 @@ static pte_t set_pte_filter(pte_t pte) 
		if (!pg)

		if (!pg)

			return pte;

			return pte;

		if (!test_bit(PG_arch_1, &pg->flags)) {

		if (!test_bit(PG_arch_1, &pg->flags)) {

#ifdef CONFIG_8xx

			/* On 8xx, cache control instructions (particularly

			 * "dcbst" from flush_dcache_icache) fault as write

			 * operation if there is an unpopulated TLB entry

			 * for the address in question. To workaround that,

			 * we invalidate the TLB here, thus avoiding dcbst

			 * misbehaviour.

			 */

			/* 8xx doesn't care about PID, size or ind args */

			_tlbil_va(addr, 0, 0, 0);

#endif /* CONFIG_8xx */

			flush_dcache_icache_page(pg);

			flush_dcache_icache_page(pg);

			set_bit(PG_arch_1, &pg->flags);

			set_bit(PG_arch_1, &pg->flags);

		}

		}
@@ -194,7 +207,7 @@ static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma, 
 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so

 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so

 * instead we "filter out" the exec permission for non clean pages.

 * instead we "filter out" the exec permission for non clean pages.

 */

 */

static pte_t set_pte_filter(pte_t pte)

static pte_t set_pte_filter(pte_t pte, unsigned long addr)

{

{

	struct page *pg;

	struct page *pg;
@@ -276,7 +289,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 
	 * this context might not have been activated yet when this

	 * this context might not have been activated yet when this

	 * is called.

	 * is called.

	 */

	 */

	pte = set_pte_filter(pte);

	pte = set_pte_filter(pte, addr);





	/* Perform the setting of the PTE */

	/* Perform the setting of the PTE */

	__set_pte_at(mm, addr, ptep, pte, 0);

	__set_pte_at(mm, addr, ptep, pte, 0);