Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit e026e700 authored by Quan Nguyen's avatar Quan Nguyen Committed by David S. Miller
Browse files

drivers: net: xgene: Fix hardware checksum setting 



This patch fixes the hardware checksum settings by properly program
the classifier. Otherwise, packet may be received with checksum error
on X-Gene1 SoC.

Signed-off-by: default avatarQuan Nguyen <qnguyen@apm.com>
Signed-off-by: default avatarIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4b72436d

drivers/net/ethernet/apm/xgene/xgene_enet_hw.c

+1 −0
Original line number Diff line number Diff line
@@ -623,6 +623,7 @@ static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata, 
	xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);

	cb |= CFG_CLE_BYPASS_EN0;

	CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);

	CFG_CLE_IP_HDR_LEN_SET(&cb, 0);

	xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);



	xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

+1 −0
Original line number Diff line number Diff line
@@ -163,6 +163,7 @@ enum xgene_enet_rm { 
#define CFG_RXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 26, 3)



#define CFG_CLE_IP_PROTOCOL0_SET(dst, val)	xgene_set_bits(dst, val, 16, 2)

#define CFG_CLE_IP_HDR_LEN_SET(dst, val)	xgene_set_bits(dst, val, 8, 5)

#define CFG_CLE_DSTQID0_SET(dst, val)		xgene_set_bits(dst, val, 0, 12)

#define CFG_CLE_FPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 16, 4)

#define CFG_CLE_NXTFPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 20, 4)