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Commit dfc14010 authored by Linus Walleij's avatar Linus Walleij Committed by Andy Gross
Browse files

ARM: dts: add SDC2 and SDC4 to the MSM8660 family 



To make the picture complete, add DTS entries also for the
second and fourth MMC/SD blocks on the MSM8660. SDC2 is
an 8-bit interface and SDC4 is a 4-bit interface.

Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 4d931755

arch/arm/boot/dts/qcom-msm8660.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -392,6 +392,21 @@ 
				cap-mmc-highspeed;

			};



			sdcc2: sdcc@12140000 {

				status		= "disabled";

				compatible	= "arm,pl18x", "arm,primecell";

				arm,primecell-periphid = <0x00051180>;

				reg		= <0x12140000 0x8000>;

				interrupts	= <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names	= "cmd_irq";

				clocks		= <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;

				clock-names	= "mclk", "apb_pclk";

				bus-width	= <8>;

				max-frequency	= <48000000>;

				cap-sd-highspeed;

				cap-mmc-highspeed;

			};



			sdcc3: sdcc@12180000 {

				compatible	= "arm,pl18x", "arm,primecell";

				arm,primecell-periphid = <0x00051180>;
@@ -408,6 +423,21 @@ 
				no-1-8-v;

			};



			sdcc4: sdcc@121c0000 {

				compatible	= "arm,pl18x", "arm,primecell";

				arm,primecell-periphid = <0x00051180>;

				status		= "disabled";

				reg		= <0x121c0000 0x8000>;

				interrupts	= <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-names	= "cmd_irq";

				clocks		= <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;

				clock-names	= "mclk", "apb_pclk";

				bus-width	= <4>;

				max-frequency	= <48000000>;

				cap-sd-highspeed;

				cap-mmc-highspeed;

			};



			sdcc5: sdcc@12200000 {

				compatible	= "arm,pl18x", "arm,primecell";

				arm,primecell-periphid = <0x00051180>;