Loading arch/arm64/boot/dts/qcom/kona-qupv3.dtsi +20 −20 Original line number Diff line number Diff line Loading @@ -42,7 +42,7 @@ qupv3_se0_i2c: i2c@980000 { compatible = "qcom,i2c-geni"; reg = <0x980000 0x4000>; interrupts = <GIC_SPI 601 0>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -62,7 +62,7 @@ qupv3_se1_i2c: i2c@984000 { compatible = "qcom,i2c-geni"; reg = <0x984000 0x4000>; interrupts = <GIC_SPI 602 0>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -82,7 +82,7 @@ qupv3_se2_i2c: i2c@988000 { compatible = "qcom,i2c-geni"; reg = <0x988000 0x4000>; interrupts = <GIC_SPI 603 0>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -102,7 +102,7 @@ qupv3_se3_i2c: i2c@98c000 { compatible = "qcom,i2c-geni"; reg = <0x98c000 0x4000>; interrupts = <GIC_SPI 604 0>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -122,7 +122,7 @@ qupv3_se4_i2c: i2c@990000 { compatible = "qcom,i2c-geni"; reg = <0x990000 0x4000>; interrupts = <GIC_SPI 605 0>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -142,7 +142,7 @@ qupv3_se5_i2c: i2c@994000 { compatible = "qcom,i2c-geni"; reg = <0x994000 0x4000>; interrupts = <GIC_SPI 606 0>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -162,7 +162,7 @@ qupv3_se6_i2c: i2c@998000 { compatible = "qcom,i2c-geni"; reg = <0x998000 0x4000>; interrupts = <GIC_SPI 607 0>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -182,7 +182,7 @@ qupv3_se7_i2c: i2c@99c000 { compatible = "qcom,i2c-geni"; reg = <0x99c000 0x4000>; interrupts = <GIC_SPI 608 0>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading Loading @@ -250,7 +250,7 @@ qupv3_se8_i2c: i2c@a80000 { compatible = "qcom,i2c-geni"; reg = <0xa80000 0x4000>; interrupts = <GIC_SPI 353 0>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -270,7 +270,7 @@ qupv3_se9_i2c: i2c@a84000 { compatible = "qcom,i2c-geni"; reg = <0xa84000 0x4000>; interrupts = <GIC_SPI 354 0>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -290,7 +290,7 @@ qupv3_se10_i2c: i2c@a88000 { compatible = "qcom,i2c-geni"; reg = <0xa88000 0x4000>; interrupts = <GIC_SPI 355 0>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -310,7 +310,7 @@ qupv3_se11_i2c: i2c@a8c000 { compatible = "qcom,i2c-geni"; reg = <0xa8c000 0x4000>; interrupts = <GIC_SPI 356 0>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -330,7 +330,7 @@ qupv3_se12_i2c: i2c@a90000 { compatible = "qcom,i2c-geni"; reg = <0xa90000 0x4000>; interrupts = <GIC_SPI 357 0>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -350,7 +350,7 @@ qupv3_se13_i2c: i2c@a94000 { compatible = "qcom,i2c-geni"; reg = <0xa94000 0x4000>; interrupts = <GIC_SPI 358 0>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading Loading @@ -386,7 +386,7 @@ qupv3_se14_i2c: i2c@880000 { compatible = "qcom,i2c-geni"; reg = <0x880000 0x4000>; interrupts = <GIC_SPI 373 0>; interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -406,7 +406,7 @@ qupv3_se15_i2c: i2c@884000 { compatible = "qcom,i2c-geni"; reg = <0x884000 0x4000>; interrupts = <GIC_SPI 583 0>; interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -426,7 +426,7 @@ qupv3_se16_i2c: i2c@888000 { compatible = "qcom,i2c-geni"; reg = <0x888000 0x4000>; interrupts = <GIC_SPI 584 0>; interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -446,7 +446,7 @@ qupv3_se17_i2c: i2c@88c000 { compatible = "qcom,i2c-geni"; reg = <0x88c000 0x4000>; interrupts = <GIC_SPI 585 0>; interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -466,7 +466,7 @@ qupv3_se18_i2c: i2c@890000 { compatible = "qcom,i2c-geni"; reg = <0x890000 0x4000>; interrupts = <GIC_SPI 586 0>; interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -486,7 +486,7 @@ qupv3_se19_i2c: i2c@894000 { compatible = "qcom,i2c-geni"; reg = <0x894000 0x4000>; interrupts = <GIC_SPI 587 0>; interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading arch/arm64/boot/dts/qcom/kona.dtsi +35 −11 Original line number Diff line number Diff line Loading @@ -610,7 +610,8 @@ reg = <0x3ac0000 0x2c000>, <0x3a84000 0x2c000>; reg-names = "slimbus_physical", "slimbus_bam_physical"; interrupts = <0 163 0>, <0 164 0>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "slimbus_irq", "slimbus_bam_irq"; qcom,apps-ch-pipes = <0x700000>; qcom,ea-pc = <0x2d0>; Loading Loading @@ -2558,10 +2559,19 @@ compatible = "qcom,gpi-dma"; reg = <0x900000 0x70000>; reg-names = "gpi-top"; interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>, <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>, <0 256 0>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; qcom,max-num-gpii = <13>; qcom,gpii-mask = <0x7ff>; qcom,ev-factor = <2>; Loading @@ -2576,9 +2586,16 @@ compatible = "qcom,gpi-dma"; reg = <0xa00000 0x70000>; reg-names = "gpi-top"; interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>, <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>, <0 295 0>, <0 296 0>; interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; qcom,max-num-gpii = <10>; qcom,gpii-mask = <0x3f>; qcom,ev-factor = <2>; Loading @@ -2593,9 +2610,16 @@ compatible = "qcom,gpi-dma"; reg = <0x800000 0x70000>; reg-names = "gpi-top"; interrupts = <0 588 0>, <0 589 0>, <0 590 0>, <0 591 0>, <0 592 0>, <0 593 0>, <0 594 0>, <0 595 0>, <0 596 0>, <0 597 0>; interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; qcom,max-num-gpii = <10>; qcom,gpii-mask = <0x3f>; qcom,ev-factor = <2>; Loading Loading
arch/arm64/boot/dts/qcom/kona-qupv3.dtsi +20 −20 Original line number Diff line number Diff line Loading @@ -42,7 +42,7 @@ qupv3_se0_i2c: i2c@980000 { compatible = "qcom,i2c-geni"; reg = <0x980000 0x4000>; interrupts = <GIC_SPI 601 0>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -62,7 +62,7 @@ qupv3_se1_i2c: i2c@984000 { compatible = "qcom,i2c-geni"; reg = <0x984000 0x4000>; interrupts = <GIC_SPI 602 0>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -82,7 +82,7 @@ qupv3_se2_i2c: i2c@988000 { compatible = "qcom,i2c-geni"; reg = <0x988000 0x4000>; interrupts = <GIC_SPI 603 0>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -102,7 +102,7 @@ qupv3_se3_i2c: i2c@98c000 { compatible = "qcom,i2c-geni"; reg = <0x98c000 0x4000>; interrupts = <GIC_SPI 604 0>; interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -122,7 +122,7 @@ qupv3_se4_i2c: i2c@990000 { compatible = "qcom,i2c-geni"; reg = <0x990000 0x4000>; interrupts = <GIC_SPI 605 0>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -142,7 +142,7 @@ qupv3_se5_i2c: i2c@994000 { compatible = "qcom,i2c-geni"; reg = <0x994000 0x4000>; interrupts = <GIC_SPI 606 0>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -162,7 +162,7 @@ qupv3_se6_i2c: i2c@998000 { compatible = "qcom,i2c-geni"; reg = <0x998000 0x4000>; interrupts = <GIC_SPI 607 0>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -182,7 +182,7 @@ qupv3_se7_i2c: i2c@99c000 { compatible = "qcom,i2c-geni"; reg = <0x99c000 0x4000>; interrupts = <GIC_SPI 608 0>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading Loading @@ -250,7 +250,7 @@ qupv3_se8_i2c: i2c@a80000 { compatible = "qcom,i2c-geni"; reg = <0xa80000 0x4000>; interrupts = <GIC_SPI 353 0>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -270,7 +270,7 @@ qupv3_se9_i2c: i2c@a84000 { compatible = "qcom,i2c-geni"; reg = <0xa84000 0x4000>; interrupts = <GIC_SPI 354 0>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -290,7 +290,7 @@ qupv3_se10_i2c: i2c@a88000 { compatible = "qcom,i2c-geni"; reg = <0xa88000 0x4000>; interrupts = <GIC_SPI 355 0>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -310,7 +310,7 @@ qupv3_se11_i2c: i2c@a8c000 { compatible = "qcom,i2c-geni"; reg = <0xa8c000 0x4000>; interrupts = <GIC_SPI 356 0>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -330,7 +330,7 @@ qupv3_se12_i2c: i2c@a90000 { compatible = "qcom,i2c-geni"; reg = <0xa90000 0x4000>; interrupts = <GIC_SPI 357 0>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -350,7 +350,7 @@ qupv3_se13_i2c: i2c@a94000 { compatible = "qcom,i2c-geni"; reg = <0xa94000 0x4000>; interrupts = <GIC_SPI 358 0>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading Loading @@ -386,7 +386,7 @@ qupv3_se14_i2c: i2c@880000 { compatible = "qcom,i2c-geni"; reg = <0x880000 0x4000>; interrupts = <GIC_SPI 373 0>; interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -406,7 +406,7 @@ qupv3_se15_i2c: i2c@884000 { compatible = "qcom,i2c-geni"; reg = <0x884000 0x4000>; interrupts = <GIC_SPI 583 0>; interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -426,7 +426,7 @@ qupv3_se16_i2c: i2c@888000 { compatible = "qcom,i2c-geni"; reg = <0x888000 0x4000>; interrupts = <GIC_SPI 584 0>; interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -446,7 +446,7 @@ qupv3_se17_i2c: i2c@88c000 { compatible = "qcom,i2c-geni"; reg = <0x88c000 0x4000>; interrupts = <GIC_SPI 585 0>; interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -466,7 +466,7 @@ qupv3_se18_i2c: i2c@890000 { compatible = "qcom,i2c-geni"; reg = <0x890000 0x4000>; interrupts = <GIC_SPI 586 0>; interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading @@ -486,7 +486,7 @@ qupv3_se19_i2c: i2c@894000 { compatible = "qcom,i2c-geni"; reg = <0x894000 0x4000>; interrupts = <GIC_SPI 587 0>; interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clock-names = "se-clk", "m-ahb", "s-ahb"; Loading
arch/arm64/boot/dts/qcom/kona.dtsi +35 −11 Original line number Diff line number Diff line Loading @@ -610,7 +610,8 @@ reg = <0x3ac0000 0x2c000>, <0x3a84000 0x2c000>; reg-names = "slimbus_physical", "slimbus_bam_physical"; interrupts = <0 163 0>, <0 164 0>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "slimbus_irq", "slimbus_bam_irq"; qcom,apps-ch-pipes = <0x700000>; qcom,ea-pc = <0x2d0>; Loading Loading @@ -2558,10 +2559,19 @@ compatible = "qcom,gpi-dma"; reg = <0x900000 0x70000>; reg-names = "gpi-top"; interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>, <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>, <0 256 0>; interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; qcom,max-num-gpii = <13>; qcom,gpii-mask = <0x7ff>; qcom,ev-factor = <2>; Loading @@ -2576,9 +2586,16 @@ compatible = "qcom,gpi-dma"; reg = <0xa00000 0x70000>; reg-names = "gpi-top"; interrupts = <0 279 0>, <0 280 0>, <0 281 0>, <0 282 0>, <0 283 0>, <0 284 0>, <0 293 0>, <0 294 0>, <0 295 0>, <0 296 0>; interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; qcom,max-num-gpii = <10>; qcom,gpii-mask = <0x3f>; qcom,ev-factor = <2>; Loading @@ -2593,9 +2610,16 @@ compatible = "qcom,gpi-dma"; reg = <0x800000 0x70000>; reg-names = "gpi-top"; interrupts = <0 588 0>, <0 589 0>, <0 590 0>, <0 591 0>, <0 592 0>, <0 593 0>, <0 594 0>, <0 595 0>, <0 596 0>, <0 597 0>; interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; qcom,max-num-gpii = <10>; qcom,gpii-mask = <0x3f>; qcom,ev-factor = <2>; Loading