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Commit df77cd83 authored by Michał Winiarski's avatar Michał Winiarski Committed by Chris Wilson
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drm/i915: Extract "emit write" part of emit breadcrumb functions 



Let's separate the "emit" part from touching any internal structures,
this way we can have a generic "emit coherent GGTT write" function.
We would like to reuse this functionality for emitting HWSP write, to
confirm that preempt-to-idle has finished.

v2: Reorder args to match emit_pipe_control, s/render/rcs (Chris)

Signed-off-by: default avatarMichał Winiarski <michal.winiarski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20171025200020.16636-8-michal.winiarski@intel.com
parent a0991e1d

drivers/gpu/drm/i915/intel_lrc.c

+8 −20
Original line number Diff line number Diff line
@@ -1794,10 +1794,8 @@ static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs) 
	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */

	BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));



	*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;

	*cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT;

	*cs++ = 0;

	*cs++ = request->global_seqno;

	cs = gen8_emit_ggtt_write(cs, request->global_seqno,

				  intel_hws_seqno_address(request->engine));

	*cs++ = MI_USER_INTERRUPT;

	*cs++ = MI_NOOP;

	request->tail = intel_ring_offset(request, cs);
@@ -1807,24 +1805,14 @@ static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs) 
}

static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;



static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,

static void gen8_emit_breadcrumb_rcs(struct drm_i915_gem_request *request,

					u32 *cs)

{

	/* We're using qword write, seqno should be aligned to 8 bytes. */

	BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);



	/* w/a for post sync ops following a GPGPU operation we

	 * need a prior CS_STALL, which is emitted by the flush

	 * following the batch.

	 */

	*cs++ = GFX_OP_PIPE_CONTROL(6);

	*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |

		PIPE_CONTROL_QW_WRITE;

	*cs++ = intel_hws_seqno_address(request->engine);

	*cs++ = 0;

	*cs++ = request->global_seqno;

	/* We're thrashing one dword of HWS. */

	*cs++ = 0;

	cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,

				      intel_hws_seqno_address(request->engine));

	*cs++ = MI_USER_INTERRUPT;

	*cs++ = MI_NOOP;

	request->tail = intel_ring_offset(request, cs);
@@ -1832,7 +1820,7 @@ static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, 


	gen8_emit_wa_tail(request, cs);

}

static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;

static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;



static int gen8_init_rcs_context(struct drm_i915_gem_request *req)

{
@@ -1991,8 +1979,8 @@ int logical_render_ring_init(struct intel_engine_cs *engine) 
		engine->init_hw = gen8_init_render_ring;

	engine->init_context = gen8_init_rcs_context;

	engine->emit_flush = gen8_emit_flush_render;

	engine->emit_breadcrumb = gen8_emit_breadcrumb_render;

	engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;

	engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;

	engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;



	ret = intel_engine_create_scratch(engine, PAGE_SIZE);

	if (ret)

drivers/gpu/drm/i915/intel_ringbuffer.h

+38 −0
Original line number Diff line number Diff line
@@ -869,6 +869,44 @@ static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) 
	return batch + 6;

}



static inline u32 *

gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset)

{

	/* We're using qword write, offset should be aligned to 8 bytes. */

	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));



	/* w/a for post sync ops following a GPGPU operation we

	 * need a prior CS_STALL, which is emitted by the flush

	 * following the batch.

	 */

	*cs++ = GFX_OP_PIPE_CONTROL(6);

	*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |

		PIPE_CONTROL_QW_WRITE;

	*cs++ = gtt_offset;

	*cs++ = 0;

	*cs++ = value;

	/* We're thrashing one dword of HWS. */

	*cs++ = 0;



	return cs;

}



static inline u32 *

gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset)

{

	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */

	GEM_BUG_ON(gtt_offset & (1 << 5));

	/* Offset should be aligned to 8 bytes for both (QW/DW) write types */

	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));



	*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;

	*cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;

	*cs++ = 0;

	*cs++ = value;



	return cs;

}



bool intel_engine_is_idle(struct intel_engine_cs *engine);

bool intel_engines_are_idle(struct drm_i915_private *dev_priv);