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Commit df5c7386 authored by Andy Shevchenko's avatar Andy Shevchenko Committed by Vinod Koul
Browse files

dmaengine: dw: some Intel devices has no memcpy support 



Provide a flag to choose if the device does support memory-to-memory transfers.
At least this is not true for iDMA32 controller that might be supported in the
future. Besides that Intel BayTrail and Braswell users should not try this
feature due to HW specific behaviour.

Signed-off-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarVinod Koul <vinod.koul@intel.com>
parent 175267b3

drivers/dma/dw/core.c

+5 −1
Original line number Diff line number Diff line
@@ -1541,6 +1541,7 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) 


		/* Fill platform data with the default values */

		pdata->is_private = true;

		pdata->is_memcpy = true;

		pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING;

		pdata->chan_priority = CHAN_PRIORITY_ASCENDING;

	} else if (pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) {
@@ -1653,10 +1654,13 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata) 
	dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);

	dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);



	dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);

	/* Set capabilities */

	dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);

	if (pdata->is_private)

		dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);

	if (pdata->is_memcpy)

		dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);



	dw->dma.dev = chip->dev;

	dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;

	dw->dma.device_free_chan_resources = dwc_free_chan_resources;

include/linux/platform_data/dma-dw.h

+2 −0
Original line number Diff line number Diff line
@@ -37,6 +37,7 @@ struct dw_dma_slave { 
 * @nr_channels: Number of channels supported by hardware (max 8)

 * @is_private: The device channels should be marked as private and not for

 *	by the general purpose DMA channel allocator.

 * @is_memcpy: The device channels do support memory-to-memory transfers.

 * @chan_allocation_order: Allocate channels starting from 0 or 7

 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.

 * @block_size: Maximum block size supported by the controller
@@ -47,6 +48,7 @@ struct dw_dma_slave { 
struct dw_dma_platform_data {

	unsigned int	nr_channels;

	bool		is_private;

	bool		is_memcpy;

#define CHAN_ALLOCATION_ASCENDING	0	/* zero to seven */

#define CHAN_ALLOCATION_DESCENDING	1	/* seven to zero */

	unsigned char	chan_allocation_order;