Merge branch 'drm-next-4.16' of git://people.freedesktop.org/~agd5f/linux into drm-next

F:	drivers/gpu/drm/tinydrm/

F:	include/drm/tinydrm/

DRM TTM SUBSYSTEM

M:	Christian Koenig <christian.koenig@amd.com>

M:	Roger He <Hongbo.He@amd.com>

T:	git git://people.freedesktop.org/~agd5f/linux

S:	Maintained

L:	dri-devel@lists.freedesktop.org

F:	include/drm/ttm/

F:	drivers/gpu/drm/ttm/

DSBR100 USB FM RADIO DRIVER

M:	Alexey Klimov <klimov.linux@gmail.com>

L:	linux-media@vger.kernel.org

	bool

	depends on DRM && MMU

config DRM_SCHED

	tristate

	depends on DRM

source "drivers/gpu/drm/i2c/Kconfig"

source "drivers/gpu/drm/arm/Kconfig"

	depends on DRM && PCI && MMU

	select FW_LOADER

        select DRM_KMS_HELPER

	select DRM_SCHED

        select DRM_TTM

	select POWER_SUPPLY

	select HWMON

obj-$(CONFIG_DRM_TINYDRM) += tinydrm/

obj-$(CONFIG_DRM_PL111) += pl111/

obj-$(CONFIG_DRM_TVE200) += tve200/

obj-$(CONFIG_DRM_SCHED)	+= scheduler/

	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \

	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \

	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \

	amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o

	amdgpu_queue_mgr.o amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o

# add asic specific block

amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \

amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o

amdgpu-y += \

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o

# add GMC block

amdgpu-y += \

amdgpu-y += amdgpu_cgs.o

# GPU scheduler

amdgpu-y += \

	../scheduler/gpu_scheduler.o \

	../scheduler/sched_fence.o \

	amdgpu_job.o

amdgpu-y += amdgpu_job.o

# ACP componet

ifneq ($(CONFIG_DRM_AMD_ACP),)

#include <drm/drmP.h>

#include <drm/drm_gem.h>

#include <drm/amdgpu_drm.h>

#include <drm/gpu_scheduler.h>

#include <kgd_kfd_interface.h>

#include "dm_pp_interface.h"

#include "amdgpu_vcn.h"

#include "amdgpu_mn.h"

#include "amdgpu_dm.h"

#include "gpu_scheduler.h"

#include "amdgpu_virt.h"

#include "amdgpu_gart.h"

#include "amdgpu_debugfs.h"

/*

 * Modules parameters.

extern int amdgpu_job_hang_limit;

extern int amdgpu_lbpw;

extern int amdgpu_compute_multipipe;

extern int amdgpu_gpu_recovery;

#ifdef CONFIG_DRM_AMDGPU_SI

extern int amdgpu_si_support;

	AMDGPU_CP_KIQ_IRQ_LAST

};

int amdgpu_set_clockgating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,

					   enum amd_ip_block_type block_type,

					   enum amd_clockgating_state state);

int amdgpu_set_powergating_state(struct amdgpu_device *adev,

int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,

					   enum amd_ip_block_type block_type,

					   enum amd_powergating_state state);

void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);

int amdgpu_wait_for_idle(struct amdgpu_device *adev,

void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,

					    u32 *flags);

int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,

				   enum amd_ip_block_type block_type);

bool amdgpu_is_idle(struct amdgpu_device *adev,

bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,

			      enum amd_ip_block_type block_type);

#define AMDGPU_MAX_IP_NUM 16

	const struct amdgpu_ip_block_version *version;

};

int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,

int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev,

				       enum amd_ip_block_type type,

				       u32 major, u32 minor);

struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,

struct amdgpu_ip_block *

amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev,

			      enum amd_ip_block_type type);

int amdgpu_ip_block_add(struct amdgpu_device *adev,

int amdgpu_device_ip_block_add(struct amdgpu_device *adev,

			       const struct amdgpu_ip_block_version *ip_block_version);

/* provided by hw blocks that can move/clear data.  e.g., gfx or sdma */

	uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,

				     uint32_t flags);

	/* get the pde for a given mc addr */

	u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);

	void (*get_vm_pde)(struct amdgpu_device *adev, int level,

			   u64 *dst, u64 *flags);

	uint32_t (*get_invalidate_req)(unsigned int vm_id);

};

	struct page	*page;

	dma_addr_t	addr;

};

int amdgpu_dummy_page_init(struct amdgpu_device *adev);

void amdgpu_dummy_page_fini(struct amdgpu_device *adev);

/*

 * Clocks

void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);

void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);

int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);

int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);

/* sub-allocation manager, it has to be protected by another lock.

 * By conception this is an helper for other part of the driver

	u64					private_aperture_end;

	/* protects concurrent invalidation */

	spinlock_t		invalidate_lock;

	bool			translate_further;

};

/*

	AMDGPU_DOORBELL64_INVALID                 = 0xFFFF

} AMDGPU_DOORBELL64_ASSIGNMENT;

void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,

				phys_addr_t *aperture_base,

				size_t *aperture_size,

				size_t *start_offset);

/*

 * IRQS.

 */

	uint32_t			flags;

};

extern const struct amd_sched_backend_ops amdgpu_sched_ops;

extern const struct drm_sched_backend_ops amdgpu_sched_ops;

int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,

		     struct amdgpu_job **job, struct amdgpu_vm *vm);

void amdgpu_job_free_resources(struct amdgpu_job *job);

void amdgpu_job_free(struct amdgpu_job *job);

int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,

		      struct amd_sched_entity *entity, void *owner,

		      struct drm_sched_entity *entity, void *owner,

		      struct dma_fence **f);

/*

struct amdgpu_ctx_ring {

	uint64_t		sequence;

	struct dma_fence	**fences;

	struct amd_sched_entity	entity;

	struct drm_sched_entity	entity;

};

struct amdgpu_ctx {

	struct dma_fence	**fences;

	struct amdgpu_ctx_ring	rings[AMDGPU_MAX_RINGS];

	bool			preamble_presented;

	enum amd_sched_priority init_priority;

	enum amd_sched_priority override_priority;

	enum drm_sched_priority init_priority;

	enum drm_sched_priority override_priority;

	struct mutex            lock;

	atomic_t	guilty;

};

struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,

				   struct amdgpu_ring *ring, uint64_t seq);

void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,

				  enum amd_sched_priority priority);

				  enum drm_sched_priority priority);

int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,

		     struct drm_file *filp);

#define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */

struct amdgpu_job {

	struct amd_sched_job    base;

	struct drm_sched_job    base;

	struct amdgpu_device	*adev;

	struct amdgpu_vm	*vm;

	struct amdgpu_ring	*ring;

	unsigned long		used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];

};

int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);

void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);

int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb);

void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb);

void amdgpu_get_pcie_info(struct amdgpu_device *adev);

void amdgpu_device_get_pcie_info(struct amdgpu_device *adev);

/*

 * SDMA

 */

void amdgpu_test_moves(struct amdgpu_device *adev);

/*

 * Debugfs

 */

struct amdgpu_debugfs {

	const struct drm_info_list	*files;

	unsigned		num_files;

};

int amdgpu_debugfs_add_files(struct amdgpu_device *adev,

			     const struct drm_info_list *files,

			     unsigned nfiles);

int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);

#if defined(CONFIG_DEBUG_FS)

int amdgpu_debugfs_init(struct drm_minor *minor);

#endif

int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);

/*

 * amdgpu smumgr functions

	void *va;

};

int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);

void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev);

/*

 * CGS

 */

typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);

typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);

/*

 * amdgpu nbio functions

 *

 */

struct nbio_hdp_flush_reg {

	u32 ref_and_mask_cp0;

	u32 ref_and_mask_cp1;

	u32 ref_and_mask_cp2;

	u32 ref_and_mask_cp3;

	u32 ref_and_mask_cp4;

	u32 ref_and_mask_cp5;

	u32 ref_and_mask_cp6;

	u32 ref_and_mask_cp7;

	u32 ref_and_mask_cp8;

	u32 ref_and_mask_cp9;

	u32 ref_and_mask_sdma0;

	u32 ref_and_mask_sdma1;

};

struct amdgpu_nbio_funcs {

	const struct nbio_hdp_flush_reg *hdp_flush_reg;

	u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev);

	u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev);

	u32 (*get_pcie_index_offset)(struct amdgpu_device *adev);

	u32 (*get_pcie_data_offset)(struct amdgpu_device *adev);

	u32 (*get_rev_id)(struct amdgpu_device *adev);

	void (*mc_access_enable)(struct amdgpu_device *adev, bool enable);

	void (*hdp_flush)(struct amdgpu_device *adev);

	u32 (*get_memsize)(struct amdgpu_device *adev);

	void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance,

				    bool use_doorbell, int doorbell_index);

	void (*enable_doorbell_aperture)(struct amdgpu_device *adev,

					 bool enable);

	void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev,

						  bool enable);

	void (*ih_doorbell_range)(struct amdgpu_device *adev,

				  bool use_doorbell, int doorbell_index);

	void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,

						 bool enable);

	void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,

						bool enable);

	void (*get_clockgating_state)(struct amdgpu_device *adev,

				      u32 *flags);

	void (*ih_control)(struct amdgpu_device *adev);

	void (*init_registers)(struct amdgpu_device *adev);

	void (*detect_hw_virt)(struct amdgpu_device *adev);

};

/* Define the HW IP blocks will be used in driver , add more if necessary */

enum amd_hw_ip_block_type {

	GC_HWIP = 1,

	HDP_HWIP,

	SDMA0_HWIP,

	SDMA1_HWIP,

	MMHUB_HWIP,

	ATHUB_HWIP,

	NBIO_HWIP,

	MP0_HWIP,

	UVD_HWIP,

	VCN_HWIP = UVD_HWIP,

	VCE_HWIP,

	DF_HWIP,

	DCE_HWIP,

	OSSSYS_HWIP,

	SMUIO_HWIP,

	PWR_HWIP,

	NBIF_HWIP,

	MAX_HWIP

};

#define HWIP_MAX_INSTANCE	6

struct amd_powerplay {

	struct cgs_device *cgs_device;

	void *pp_handle;

	/* amdkfd interface */

	struct kfd_dev          *kfd;

	/* soc15 register offset based on ip, instance and  segment */

	uint32_t 		*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];

	const struct amdgpu_nbio_funcs	*nbio_funcs;

	/* delayed work_func for deferring clockgating during resume */

	struct delayed_work     late_init_work;

#define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))

#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))

#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))

#define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))

#define amdgpu_gart_get_vm_pde(adev, level, dst, flags) (adev)->gart.gart_funcs->get_vm_pde((adev), (level), (dst), (flags))

#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))

#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))

#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))

#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))

/* Common functions */

int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job* job);

bool amdgpu_need_backup(struct amdgpu_device *adev);

void amdgpu_pci_config_reset(struct amdgpu_device *adev);

bool amdgpu_need_post(struct amdgpu_device *adev);

int amdgpu_device_gpu_recover(struct amdgpu_device *adev,

			      struct amdgpu_job* job, bool force);

void amdgpu_device_pci_config_reset(struct amdgpu_device *adev);

bool amdgpu_device_need_post(struct amdgpu_device *adev);

void amdgpu_update_display_priority(struct amdgpu_device *adev);

void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,

				  u64 num_vis_bytes);

void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);

bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);

void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);

void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);

void amdgpu_device_vram_location(struct amdgpu_device *adev,

				 struct amdgpu_mc *mc, u64 base);

void amdgpu_device_gart_location(struct amdgpu_device *adev,

				 struct amdgpu_mc *mc);

int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);

void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);

int amdgpu_ttm_init(struct amdgpu_device *adev);

void amdgpu_ttm_fini(struct amdgpu_device *adev);

void amdgpu_program_register_sequence(struct amdgpu_device *adev,

void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,

					     const u32 *registers,

					     const u32 array_size);

int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);

void amdgpu_driver_postclose_kms(struct drm_device *dev,

				 struct drm_file *file_priv);

int amdgpu_suspend(struct amdgpu_device *adev);

int amdgpu_device_ip_suspend(struct amdgpu_device *adev);

int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);

int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);

u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);