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Commit deeb1519 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Document and reject invalid tiling modes 



Through the GTT interface to the fence registers, we can only handle
linear, X and Y tiling. The more esoteric tiling patterns are ignored.
Document that the tiling ABI only supports upto Y tiling, and reject any
attempts to set a tiling mode other than NONE, X or Y.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1470388464-28458-17-git-send-email-chris@chris-wilson.co.uk
parent 9ad36761

drivers/gpu/drm/i915/i915_gem_tiling.c

+3 −0
Original line number Diff line number Diff line
@@ -68,6 +68,9 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) 
	if (tiling_mode == I915_TILING_NONE)

		return true;



	if (tiling_mode > I915_TILING_LAST)

		return false;



	if (IS_GEN2(dev) ||

	    (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))

		tile_width = 128;

include/uapi/drm/i915_drm.h

+1 −0
Original line number Diff line number Diff line
@@ -926,6 +926,7 @@ struct drm_i915_gem_caching { 
#define I915_TILING_NONE	0

#define I915_TILING_X		1

#define I915_TILING_Y		2

#define I915_TILING_LAST	I915_TILING_Y



#define I915_BIT_6_SWIZZLE_NONE		0

#define I915_BIT_6_SWIZZLE_9		1