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Commit de536a01 authored by Amir Samuelov's avatar Amir Samuelov Committed by Gerrit - the friendly Code Review server
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dt-bindings: spss_utils: add new properties for IAR 

Add properties to read IAR_FEATURE_ENABLE soc fuse.
Add properties to calculate IAR-Memory address,
which follows SPU PIL-Memory region.

Change-Id: I9c9606250c2a12ca3fbfdd189b5890b12ea9b860
parent 5054306d

bindings/arm/msm/spss_utils.txt

+30 −12
Original line number Diff line number Diff line
@@ -9,29 +9,47 @@ The communication with SPSS is done via spcom driver, using glink. 
The spss_utils driver selects the SPSS firmware file,

according to a dedicated fuse and the platform HW version.



The spss_utils driver supports SPU Insider Attack Resistance (IAR) Feature.

SPU ROM code (PBL) expects a unique cmac for the spu firmware and spu apps.

The spss_utils driver registers an IAR callback to the PIL notification driver.

When SPU reset detected (SSR) the PIL calls the IAR callback to place the

required cmac in shared memory in DDR.



Required properties:

-compatible : should be "qcom,spss_utils"

-qcom,spss-fuse1-addr: fuse1 register physical address

-qcom,spss-fuse1-bit: fuse1 relevant bit

-qcom,spss-fuse2-addr: fuse2 register physical address

-qcom,spss-fuse2-bit: fuse2 relevant bit

-qcom,spss-fuse3-addr: fuse3 register physical address

-qcom,spss-fuse3-bit: fuse3 relevant bit

-qcom,spss-fuse4-addr: fuse4 register physical address

-qcom,spss-fuse4-bit: fuse4 relevant bit

-qcom,spss-dev-firmware-name: dev firmware file name

-qcom,spss-test-firmware-name: test firmware file name

-qcom,spss-prod-firmware-name: production firmware file name

-qcom,spss-debug-reg-addr: debug register physical address

-qcom,spss-emul-type-reg-addr: soc emulation type register physical address

-qcom,pil-mem: pointer to pil_spss_mem node, to get PIL memory address

-qcom,pil-mem: PIL memory size, spu firmware size is padded to 960 KB



Example:

   qcom,spss_utils {

spss_utils: qcom,spss_utils {

	compatible = "qcom,spss-utils";



      qcom,spss-fuse1-addr = <0x007841c4>;

	qcom,spss-fuse1-addr = <0x00780234>;

	qcom,spss-fuse1-bit = <27>;

      qcom,spss-fuse2-addr = <0x007841c4>;

	qcom,spss-fuse2-addr = <0x00780234>;

	qcom,spss-fuse2-bit = <26>;

	qcom,spss-fuse3-addr = <0x007801E8>;

	qcom,spss-fuse3-bit = <10>;

	qcom,spss-fuse4-addr = <0x00780218>;

	qcom,spss-fuse4-bit = <1>;

	qcom,spss-dev-firmware-name  = "spss1d";  /* 8 chars max */

	qcom,spss-test-firmware-name = "spss1t";  /* 8 chars max */

	qcom,spss-prod-firmware-name = "spss1p";  /* 8 chars max */

	qcom,spss-debug-reg-addr = <0x01886020>;

	qcom,spss-emul-type-reg-addr = <0x01fc8004>;

	pil-mem = <&pil_spss_mem>;

	qcom,pil-size = <0x0F0000>;

};