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Commit dd6ec12f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'devicetree-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull DeviceTree updates from Rob Herring:

 - vsprintf format specifier %pOF for device_node's. This will enable us
   to stop storing the full node names. Conversion of users will happen
   next cycle.

 - Update documentation to point to DT specification instead of ePAPR.

 - Split out graph and property functions to a separate file.

 - New of-graph functions for ALSA

 - Add vendor prefixes for RISC-V, Linksys, iWave Systems, Roofull,
   Itead, and BananaPi.

 - Improve dtx_diff utility filename printing.

* tag 'devicetree-for-4.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (32 commits)
  of: document /sys/firmware/fdt
  dt-bindings: Add RISC-V vendor prefix
  vsprintf: Add %p extension "%pOF" for device tree
  of: find_node_by_full_name rewrite to compare each level
  of: use kbasename instead of open coding
  dt-bindings: thermal: add file extension to brcm,ns-thermal
  of: update ePAPR references to point to Devicetree Specification
  scripts/dtc: dtx_diff - Show real file names in diff header
  of: detect invalid phandle in overlay
  of: be consistent in form of file mode
  of: make __of_attach_node() static
  of: address.c header comment typo
  of: fdt.c header comment typo
  of: make of_fdt_is_compatible() static
  dt-bindings: display-timing.txt convert non-ascii characters to ascii
  Documentation: remove overlay-notes reference to non-existent file
  dt-bindings: usb: exynos-usb: Add missing required VDD properties
  dt-bindings: Add vendor prefix for Linksys
  MAINTAINERS: add device tree ABI documentation file
  of: Add vendor prefix for iWave Systems Technologies Pvt. Ltd
  ...
parents 21c19bc7 a4485b54

Documentation/ABI/testing/sysfs-firmware-ofw

+25 −1
Original line number Diff line number Diff line 
What:		/sys/firmware/devicetree/*

Date:		November 2013

Contact:	Grant Likely <grant.likely@linaro.org>

Contact:	Grant Likely <grant.likely@arm.com>, devicetree@vger.kernel.org

Description:

		When using OpenFirmware or a Flattened Device Tree to enumerate

		hardware, the device tree structure will be exposed in this
@@ -26,3 +26,27 @@ Description: 
		name plus address). Properties are represented as files

		in the directory. The contents of each file is the exact

		binary data from the device tree.



What:		/sys/firmware/fdt

Date:		February 2015

KernelVersion:	3.19

Contact:	Frank Rowand <frowand.list@gmail.com>, devicetree@vger.kernel.org

Description:

		Exports the FDT blob that was passed to the kernel by

		the bootloader. This allows userland applications such

		as kexec to access the raw binary. This blob is also

		useful when debugging since it contains any changes

		made to the blob by the bootloader.



		The fact that this node does not reside under

		/sys/firmware/device-tree is deliberate: FDT is also used

		on arm64 UEFI/ACPI systems to communicate just the UEFI

		and ACPI entry points, but the FDT is never unflattened

		and used to configure the system.



		A CRC32 checksum is calculated over the entire FDT

		blob, and verified at late_initcall time. The sysfs

		entry is instantiated only if the checksum is valid,

		i.e., if the FDT blob has not been modified in the mean

		time. Otherwise, a warning is printed.

Users:		kexec, debugging

Documentation/devicetree/bindings/arm/cci.txt

+4 −11
Original line number Diff line number Diff line
@@ -11,13 +11,6 @@ clusters, through memory mapped interface, with a global control register 
space and multiple sets of interface control registers, one per slave

interface.



Bindings for the CCI node follow the ePAPR standard, available from:



www.power.org/documentation/epapr-version-1-1/



with the addition of the bindings described in this document which are

specific to ARM.



* CCI interconnect node



	Description: Describes a CCI cache coherent Interconnect component
@@ -50,10 +43,10 @@ specific to ARM. 
			    as a tuple of cells, containing child address,

			    parent address and the size of the region in the

			    child address space.

		Definition: A standard property. Follow rules in the ePAPR for

			    hierarchical bus addressing. CCI interfaces

			    addresses refer to the parent node addressing

			    scheme to declare their register bases.

		Definition: A standard property. Follow rules in the Devicetree

			    Specification for hierarchical bus addressing. CCI

			    interfaces addresses refer to the parent node

			    addressing scheme to declare their register bases.



	CCI interconnect node can define the following child nodes:

Documentation/devicetree/bindings/arm/cpus.txt

+7 −6
Original line number Diff line number Diff line
@@ -6,9 +6,9 @@ The device tree allows to describe the layout of CPUs in a system through 
the "cpus" node, which in turn contains a number of subnodes (ie "cpu")

defining properties for every cpu.



Bindings for CPU nodes follow the ePAPR v1.1 standard, available from:

Bindings for CPU nodes follow the Devicetree Specification, available from:



https://www.power.org/documentation/epapr-version-1-1/

https://www.devicetree.org/specifications/



with updates for 32-bit and 64-bit ARM systems provided in this document.
@@ -16,8 +16,8 @@ with updates for 32-bit and 64-bit ARM systems provided in this document. 
Convention used in this document

================================



This document follows the conventions described in the ePAPR v1.1, with

the addition:

This document follows the conventions described in the Devicetree

Specification, with the addition:



- square brackets define bitfields, eg reg[7:0] value of the bitfield in

  the reg property contained in bits 7 down to 0
@@ -26,8 +26,9 @@ the addition: 
cpus and cpu node bindings definition

=====================================



The ARM architecture, in accordance with the ePAPR, requires the cpus and cpu

nodes to be present and contain the properties described below.

The ARM architecture, in accordance with the Devicetree Specification,

requires the cpus and cpu nodes to be present and contain the properties

described below.



- cpus node

Documentation/devicetree/bindings/arm/idle-states.txt

+2 −2
Original line number Diff line number Diff line
@@ -695,5 +695,5 @@ cpus { 
[4] ARM Architecture Reference Manuals

    http://infocenter.arm.com/help/index.jsp



[5] ePAPR standard

    https://www.power.org/documentation/epapr-version-1-1/
 
[5] Devicetree Specification

    https://www.devicetree.org/specifications/

Documentation/devicetree/bindings/arm/l2c2x0.txt

+2 −2
Original line number Diff line number Diff line
@@ -4,8 +4,8 @@ ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/ 
PL310 and variants) based level 2 cache controller. All these various implementations

of the L2 cache controller have compatible programming models (Note 1).

Some of the properties that are just prefixed "cache-*" are taken from section

3.7.3 of the ePAPR v1.1 specification which can be found at:

https://www.power.org/wp-content/uploads/2012/06/Power_ePAPR_APPROVED_v1.1.pdf

3.7.3 of the Devicetree Specification which can be found at:

https://www.devicetree.org/specifications/



The ARM L2 cache representation in the device tree should be done as follows: