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Commit dd53a421 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull misc x86 fixes from Ingo Molnar:

 - make CR4 handling irq-safe, which bug vmware guests ran into

 - don't crash on early IRQs in Xen guests

 - don't crash secondary CPU bringup if #UD assisted WARN()ings are
   triggered

 - make X86_BUG_FXSAVE_LEAK optional on newer AMD CPUs that have the fix

 - fix AMD Fam17h microcode loading

 - fix broadcom_postcore_init() if ACPI is disabled

 - fix resume regression in __restore_processor_context()

 - fix Sparse warnings

 - fix a GCC-8 warning

* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/vdso: Change time() prototype to match __vdso_time()
  x86: Fix Sparse warnings about non-static functions
  x86/power: Fix some ordering bugs in __restore_processor_context()
  x86/PCI: Make broadcom_postcore_init() check acpi_disabled
  x86/microcode/AMD: Add support for fam17h microcode loading
  x86/cpufeatures: Make X86_BUG_FXSAVE_LEAK detectable in CPUID on AMD
  x86/idt: Load idt early in start_secondary
  x86/xen: Support early interrupts in xen pv guests
  x86/tlb: Disable interrupts when changing CR4
  x86/tlb: Refactor CR4 setting and shadow write
parents 4b43a3bc 88edb57d

arch/x86/entry/vdso/vclock_gettime.c

+1 −1
Original line number Diff line number Diff line
@@ -324,5 +324,5 @@ notrace time_t __vdso_time(time_t *t) 
		*t = result;

	return result;

}

int time(time_t *t)

time_t time(time_t *t)

	__attribute__((weak, alias("__vdso_time")));

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -266,6 +266,7 @@ 
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */

#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

#define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */

#define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */

#define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */

arch/x86/include/asm/segment.h

+12 −0
Original line number Diff line number Diff line
@@ -236,11 +236,23 @@ 
 */

#define EARLY_IDT_HANDLER_SIZE 9



/*

 * xen_early_idt_handler_array is for Xen pv guests: for each entry in

 * early_idt_handler_array it contains a prequel in the form of

 * pop %rcx; pop %r11; jmp early_idt_handler_array[i]; summing up to

 * max 8 bytes.

 */

#define XEN_EARLY_IDT_HANDLER_SIZE 8



#ifndef __ASSEMBLY__



extern const char early_idt_handler_array[NUM_EXCEPTION_VECTORS][EARLY_IDT_HANDLER_SIZE];

extern void early_ignore_irq(void);



#if defined(CONFIG_X86_64) && defined(CONFIG_XEN_PV)

extern const char xen_early_idt_handler_array[NUM_EXCEPTION_VECTORS][XEN_EARLY_IDT_HANDLER_SIZE];

#endif



/*

 * Load a segment. Fall back on loading the zero segment if something goes

 * wrong.  This variant assumes that loading zero fully clears the segment.

arch/x86/include/asm/tlbflush.h

+19 −16
Original line number Diff line number Diff line
@@ -173,40 +173,43 @@ static inline void cr4_init_shadow(void) 
	this_cpu_write(cpu_tlbstate.cr4, __read_cr4());

}



static inline void __cr4_set(unsigned long cr4)

{

	lockdep_assert_irqs_disabled();

	this_cpu_write(cpu_tlbstate.cr4, cr4);

	__write_cr4(cr4);

}



/* Set in this cpu's CR4. */

static inline void cr4_set_bits(unsigned long mask)

{

	unsigned long cr4;

	unsigned long cr4, flags;



	local_irq_save(flags);

	cr4 = this_cpu_read(cpu_tlbstate.cr4);

	if ((cr4 | mask) != cr4) {

		cr4 |= mask;

		this_cpu_write(cpu_tlbstate.cr4, cr4);

		__write_cr4(cr4);

	}

	if ((cr4 | mask) != cr4)

		__cr4_set(cr4 | mask);

	local_irq_restore(flags);

}



/* Clear in this cpu's CR4. */

static inline void cr4_clear_bits(unsigned long mask)

{

	unsigned long cr4;

	unsigned long cr4, flags;



	local_irq_save(flags);

	cr4 = this_cpu_read(cpu_tlbstate.cr4);

	if ((cr4 & ~mask) != cr4) {

		cr4 &= ~mask;

		this_cpu_write(cpu_tlbstate.cr4, cr4);

		__write_cr4(cr4);

	}

	if ((cr4 & ~mask) != cr4)

		__cr4_set(cr4 & ~mask);

	local_irq_restore(flags);

}



static inline void cr4_toggle_bits(unsigned long mask)

static inline void cr4_toggle_bits_irqsoff(unsigned long mask)

{

	unsigned long cr4;



	cr4 = this_cpu_read(cpu_tlbstate.cr4);

	cr4 ^= mask;

	this_cpu_write(cpu_tlbstate.cr4, cr4);

	__write_cr4(cr4);

	__cr4_set(cr4 ^ mask);

}



/* Read the CR4 shadow. */

arch/x86/kernel/apic/vector.c

+2 −2
Original line number Diff line number Diff line
@@ -542,7 +542,7 @@ static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, 
}



#ifdef CONFIG_GENERIC_IRQ_DEBUGFS

void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,

static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,

				  struct irq_data *irqd, int ind)

{

	unsigned int cpu, vector, prev_cpu, prev_vector;