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Commit dd149e85 authored by Dien Pham's avatar Dien Pham Committed by Simon Horman
Browse files

arm64: dts: renesas: r8a7795: Add OPPs table for cpu devices 



Define OOP tables for all CPUs.
This allows CPUFreq to function.

Based in part on work by Hien Dang.

Signed-off-by: default avatarDien Pham <dien.pham.ry@rvc.renesas.com>
Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Tested-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
parent 1c6c924a

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+61 −0
Original line number Diff line number Diff line
@@ -41,6 +41,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA57_CPU0>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

		};



		a57_1: cpu@1 {
@@ -50,6 +52,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA57_CPU1>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

		};



		a57_2: cpu@2 {
@@ -59,6 +63,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA57_CPU2>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

		};



		a57_3: cpu@3 {
@@ -68,6 +74,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA57_CPU3>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z>;

			operating-points-v2 = <&cluster0_opp>;

		};



		a53_0: cpu@100 {
@@ -77,6 +85,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_1: cpu@101 {
@@ -86,6 +96,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_2: cpu@102 {
@@ -95,6 +107,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		a53_3: cpu@103 {
@@ -104,6 +118,8 @@ 
			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

			clocks =<&cpg CPG_CORE R8A7795_CLK_Z2>;

			operating-points-v2 = <&cluster1_opp>;

		};



		L2_CA57: cache-controller-0 {
@@ -165,6 +181,51 @@ 
		clock-frequency = <0>;

	};



	cluster0_opp: opp_table0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

		};

		opp-1500000000 {

			opp-hz = /bits/ 64 <1500000000>;

			opp-microvolt = <830000>;

			clock-latency-ns = <300000>;

			opp-suspend;

		};

		opp-1600000000 {

			opp-hz = /bits/ 64 <1600000000>;

			opp-microvolt = <900000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

		opp-1700000000 {

			opp-hz = /bits/ 64 <1700000000>;

			opp-microvolt = <960000>;

			clock-latency-ns = <300000>;

			turbo-mode;

		};

	};



	cluster1_opp: opp_table1 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <820000>;

			clock-latency-ns = <300000>;

		};

	};



	/* External PCIe clock - can be overridden by the board */

	pcie_bus_clk: pcie_bus {

		compatible = "fixed-clock";