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Commit dbc1c5fc authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'hisi-arm64-dt-for-4.14-v2' of git://github.com/hisilicon/linux-hisi into next/dt64 

Pull "ARM64: DT: Hisilicon SoC DT updates for 4.14" from Wei Xu:

- Add PCIe node for hip07
- Add acpu_sctrl node and refine the usb tx fifo size for hi6220
- Add cpu idle states, L2 cache, PMU, OP-TEE, reboot, pstore,
  k3-dma and watchdog nodes for hi3660 and hikey960
- Update mmc and bluetooth nodes for hi3660 and hikey960

* tag 'hisi-arm64-dt-for-4.14-v2' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hi3660: enable watchdog
  arm64: dts: hi3660: add bindings for DMA
  arm64: dts: hikey960: change bluetooth uart max-speed to 3mbps
  arm64: dts: hi3660: Reset the mmc hosts
  arm64: dts: hikey960: Add pstore support
  arm64: dts: hikey960: Add support for syscon-reboot-mode
  arm64: dts: hikey960: Add optee node
  arm64: dts: hi3660: add pmu dt node for hi3660
  arm64: dts: hi3660: add L2 cache topology
  arm64: dts: hi3660: enable idle states
  arm64: dts: hi6220: improve g-tx-fifo-size setting for usb device
  arm64: dts: hi6220: add acpu_sctrl
  arm64: dts: hisi: add PCIe host controller node for hip07 SoC
parents 029fb7c2 487f00d4

arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts

+36 −1
Original line number Diff line number Diff line
@@ -39,6 +39,34 @@ 
		reg = <0x0 0x0 0x0 0x0>;

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;



		ramoops@32000000 {

			compatible = "ramoops";

			reg = <0x0 0x32000000 0x0 0x00100000>;

			record-size	= <0x00020000>;

			console-size	= <0x00020000>;

			ftrace-size	= <0x00020000>;

		};

	};



	reboot-mode-syscon@32100000 {

		compatible = "syscon", "simple-mfd";

		reg = <0x0 0x32100000 0x0 0x00001000>;



		reboot-mode {

			compatible = "syscon-reboot-mode";

			offset = <0x0>;



			mode-normal	= <0x77665501>;

			mode-bootloader	= <0x77665500>;

			mode-recovery	= <0x77665502>;

		};

	};



	keys {

		compatible = "gpio-keys";

		pinctrl-names = "default";
@@ -159,6 +187,13 @@ 
		startup-delay-us = <70000>;

		enable-active-high;

	};



	firmware {

		optee {

			compatible = "linaro,optee-tz";

			method = "smc";

		};

	};

};



&i2c0 {
@@ -195,7 +230,7 @@ 
	bluetooth {

		compatible = "ti,wl1837-st";

		enable-gpios = <&gpio15 6 GPIO_ACTIVE_HIGH>;

		max-speed = <921600>;

		max-speed = <3000000>;

	};

};

arch/arm64/boot/dts/hisilicon/hi3660.dtsi

+130 −0
Original line number Diff line number Diff line
@@ -58,6 +58,8 @@ 
			device_type = "cpu";

			reg = <0x0 0x0>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;

		};



		cpu1: cpu@1 {
@@ -65,6 +67,8 @@ 
			device_type = "cpu";

			reg = <0x0 0x1>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;

		};



		cpu2: cpu@2 {
@@ -72,6 +76,8 @@ 
			device_type = "cpu";

			reg = <0x0 0x2>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;

		};



		cpu3: cpu@3 {
@@ -79,6 +85,8 @@ 
			device_type = "cpu";

			reg = <0x0 0x3>;

			enable-method = "psci";

			next-level-cache = <&A53_L2>;

			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>;

		};



		cpu4: cpu@100 {
@@ -86,6 +94,12 @@ 
			device_type = "cpu";

			reg = <0x0 0x100>;

			enable-method = "psci";

			next-level-cache = <&A73_L2>;

			cpu-idle-states = <

					&CPU_NAP

					&CPU_SLEEP

					&CLUSTER_SLEEP_1

			>;

		};



		cpu5: cpu@101 {
@@ -93,6 +107,12 @@ 
			device_type = "cpu";

			reg = <0x0 0x101>;

			enable-method = "psci";

			next-level-cache = <&A73_L2>;

			cpu-idle-states = <

					&CPU_NAP

					&CPU_SLEEP

					&CLUSTER_SLEEP_1

			>;

		};



		cpu6: cpu@102 {
@@ -100,6 +120,12 @@ 
			device_type = "cpu";

			reg = <0x0 0x102>;

			enable-method = "psci";

			next-level-cache = <&A73_L2>;

			cpu-idle-states = <

					&CPU_NAP

					&CPU_SLEEP

					&CLUSTER_SLEEP_1

			>;

		};



		cpu7: cpu@103 {
@@ -107,6 +133,59 @@ 
			device_type = "cpu";

			reg = <0x0 0x103>;

			enable-method = "psci";

			next-level-cache = <&A73_L2>;

			cpu-idle-states = <

					&CPU_NAP

					&CPU_SLEEP

					&CLUSTER_SLEEP_1

			>;

		};



		idle-states {

			entry-method = "psci";



			CPU_NAP: cpu-nap {

				compatible = "arm,idle-state";

				arm,psci-suspend-param = <0x0000001>;

				entry-latency-us = <7>;

				exit-latency-us = <2>;

				min-residency-us = <15>;

			};



			CPU_SLEEP: cpu-sleep {

				compatible = "arm,idle-state";

				local-timer-stop;

				arm,psci-suspend-param = <0x0010000>;

				entry-latency-us = <40>;

				exit-latency-us = <70>;

				min-residency-us = <3000>;

			};



			CLUSTER_SLEEP_0: cluster-sleep-0 {

				compatible = "arm,idle-state";

				local-timer-stop;

				arm,psci-suspend-param = <0x1010000>;

				entry-latency-us = <500>;

				exit-latency-us = <5000>;

				min-residency-us = <20000>;

			};



			CLUSTER_SLEEP_1: cluster-sleep-1 {

				compatible = "arm,idle-state";

				local-timer-stop;

				arm,psci-suspend-param = <0x1010000>;

				entry-latency-us = <1000>;

				exit-latency-us = <5000>;

				min-residency-us = <20000>;

			};

		};



		A53_L2: l2-cache0 {

			compatible = "cache";

		};



		A73_L2: l2-cache1 {

			compatible = "cache";

		};

	};
@@ -123,6 +202,26 @@ 
					 IRQ_TYPE_LEVEL_HIGH)>;

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&cpu0>,

				     <&cpu1>,

				     <&cpu2>,

				     <&cpu3>,

				     <&cpu4>,

				     <&cpu5>,

				     <&cpu6>,

				     <&cpu7>;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;
@@ -337,6 +436,19 @@ 
			status = "disabled";

		};



		dma0: dma@fdf30000 {

			compatible = "hisilicon,k3-dma-1.0";

			reg = <0x0 0xfdf30000 0x0 0x1000>;

			#dma-cells = <1>;

			dma-channels = <16>;

			dma-requests = <32>;

			dma-min-chan = <1>;

			interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>;

			dma-no-cci;

			dma-type = "hi3660_dma";

		};



		rtc0: rtc@fff04000 {

			compatible = "arm,pl031", "arm,primecell";

			reg = <0x0 0Xfff04000 0x0 0x1000>;
@@ -810,6 +922,7 @@ 
			clock-names = "ciu", "biu";

			clock-frequency = <3200000>;

			resets = <&crg_rst 0x94 18>;

			reset-names = "reset";

			cd-gpios = <&gpio25 3 0>;

			hisilicon,peripheral-syscon = <&sctrl>;

			pinctrl-names = "default";
@@ -839,6 +952,7 @@ 
				 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>;

			clock-names = "ciu", "biu";

			resets = <&crg_rst 0x94 20>;

			reset-names = "reset";

			card-detect-delay = <200>;

			supports-highspeed;

			keep-power-in-suspend;
@@ -848,5 +962,21 @@ 
				     &sdio_cfg_func>;

			status = "disabled";

		};



		watchdog0: watchdog@e8a06000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xe8a06000 0x0 0x1000>;

			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg_ctrl HI3660_OSC32K>;

			clock-names = "apb_pclk";

		};



		watchdog1: watchdog@e8a07000 {

			compatible = "arm,sp805-wdt", "arm,primecell";

			reg = <0x0 0xe8a07000 0x0 0x1000>;

			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&crg_ctrl HI3660_OSC32K>;

			clock-names = "apb_pclk";

		};

	};

};

arch/arm64/boot/dts/hisilicon/hi6220.dtsi

+8 −1
Original line number Diff line number Diff line
@@ -262,6 +262,12 @@ 
			#clock-cells = <1>;

		};



		acpu_sctrl: acpu_sctrl@f6504000 {

			compatible = "hisilicon,hi6220-acpu-sctrl", "syscon";

			reg = <0x0 0xf6504000 0x0 0x1000>;

			#clock-cells = <1>;

		};



		medianoc_ade: medianoc_ade@f4520000 {

			compatible = "syscon";

			reg = <0x0 0xf4520000 0x0 0x4000>;
@@ -755,7 +761,8 @@ 
			dr_mode = "otg";

			g-rx-fifo-size = <512>;

			g-np-tx-fifo-size = <128>;

			g-tx-fifo-size = <128 128 128 128 128 128>;

			g-tx-fifo-size = <128 128 128 128 128 128 128 128

					   16  16  16  16  16  16  16>;

			interrupts = <0 77 0x4>;

		};

arch/arm64/boot/dts/hisilicon/hip07-d05.dts

+4 −0
Original line number Diff line number Diff line
@@ -84,3 +84,7 @@ 
&sas1 {

	status = "ok";

};



&p0_pcie2_a {

	status = "ok";

};

arch/arm64/boot/dts/hisilicon/hip07.dtsi

+22 −0
Original line number Diff line number Diff line
@@ -1534,5 +1534,27 @@ 
				     <637 1>,<638 1>,<639 1>;

			status = "disabled";

		};



		p0_pcie2_a: pcie@a00a0000 {

			compatible = "hisilicon,hip07-pcie-ecam";

			reg = <0 0xaf800000 0 0x800000>,

			      <0 0xa00a0000 0 0x10000>;

			bus-range = <0xf8 0xff>;

			msi-map = <0xf800 &p0_its_dsa_a 0xf800 0x800>;

			msi-map-mask = <0xffff>;

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			dma-coherent;

			ranges = <0x02000000 0 0xa8000000 0 0xa8000000 0 0x77f0000

				  0x01000000 0 0 0 0xaf7f0000 0 0x10000>;

			#interrupt-cells = <1>;

			interrupt-map-mask = <0xf800 0 0 7>;

			interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4

					 0x0 0 0 2 &mbigen_pcie2_a 671 4

					 0x0 0 0 3 &mbigen_pcie2_a 671 4

					 0x0 0 0 4 &mbigen_pcie2_a 671 4>;

			status = "disabled";

		};

	};

};