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Commit da9cb11f authored by Mahesh Kumar's avatar Mahesh Kumar Committed by Rodrigo Vivi
Browse files

drm/i915/cnl: Kill _MMIO_PORT6 macro 



This patch replaces use of remaining _MMIO_PORT6 macro and removes the
macro.

Changes Since V1:
 - Rebase

Signed-off-by: default avatarMahesh Kumar <mahesh1.kumar@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180314080653.9444-3-mahesh1.kumar@intel.com
parent 4635b573

drivers/gpu/drm/i915/i915_reg.h

+5 −5
Original line number Diff line number Diff line
@@ -153,7 +153,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c))

#define _PLL(pll, a, b) ((a) + (pll)*((b)-(a)))

#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b))

#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f))

#define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__)

#define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))
@@ -1946,20 +1945,21 @@ enum i915_power_well_id { 
#define _CNL_PORT_PCS_DW1_LN0_C		0x162C04

#define _CNL_PORT_PCS_DW1_LN0_D		0x162E04

#define _CNL_PORT_PCS_DW1_LN0_F		0x162804

#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO_PORT6(port, \

#define CNL_PORT_PCS_DW1_GRP(port)	_MMIO(_PICK(port, \

						    _CNL_PORT_PCS_DW1_GRP_AE, \

						    _CNL_PORT_PCS_DW1_GRP_B, \

						    _CNL_PORT_PCS_DW1_GRP_C, \

						    _CNL_PORT_PCS_DW1_GRP_D, \

						    _CNL_PORT_PCS_DW1_GRP_AE, \

						    _CNL_PORT_PCS_DW1_GRP_F)

#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO_PORT6(port, \

						    _CNL_PORT_PCS_DW1_GRP_F))



#define CNL_PORT_PCS_DW1_LN0(port)	_MMIO(_PICK(port, \

						    _CNL_PORT_PCS_DW1_LN0_AE, \

						    _CNL_PORT_PCS_DW1_LN0_B, \

						    _CNL_PORT_PCS_DW1_LN0_C, \

						    _CNL_PORT_PCS_DW1_LN0_D, \

						    _CNL_PORT_PCS_DW1_LN0_AE, \

						    _CNL_PORT_PCS_DW1_LN0_F)

						    _CNL_PORT_PCS_DW1_LN0_F))

#define   COMMON_KEEPER_EN		(1 << 26)



/* CNL Port TX registers */