Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit da89e1d5 authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
Browse files

ARM: sunxi: h3/h5: add usb_otg and OHCI/EHCI for usbc0 on H3/H5 



Allwinner H3/H5 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
or MUSB controller.

Add device nodes for these controllers.

Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 0127216f

arch/arm/boot/dts/sunxi-h3-h5.dtsi

+32 −0
Original line number Diff line number Diff line
@@ -144,6 +144,19 @@ 
			#size-cells = <0>;

		};



		usb_otg: usb@01c19000 {

			compatible = "allwinner,sun8i-h3-musb";

			reg = <0x01c19000 0x400>;

			clocks = <&ccu CLK_BUS_OTG>;

			resets = <&ccu RST_BUS_OTG>;

			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "mc";

			phys = <&usbphy 0>;

			phy-names = "usb";

			extcon = <&usbphy 0>;

			status = "disabled";

		};



		usbphy: phy@01c19400 {

			compatible = "allwinner,sun8i-h3-usb-phy";

			reg = <0x01c19400 0x2c>,
@@ -176,6 +189,25 @@ 
			#phy-cells = <1>;

		};



		ehci0: usb@01c1a000 {

			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";

			reg = <0x01c1a000 0x100>;

			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;

			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;

			status = "disabled";

		};



		ohci0: usb@01c1a400 {

			compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";

			reg = <0x01c1a400 0x100>;

			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,

				 <&ccu CLK_USB_OHCI0>;

			resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;

			status = "disabled";

		};



		ehci1: usb@01c1b000 {

			compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";

			reg = <0x01c1b000 0x100>;