Merge "msm: kgsl: Refactor getproperty/setproperty" (da707274) · Commits · e / devices / android_kernel_oneplus_sm7250

drivers/gpu/msm/adreno.c

+56 −56

Original line number	Diff line number	Diff line
		@@ -38,9 +38,6 @@
		#include "adreno-gpulist.h"
		#include "adreno_dispatch.h"

		#define DRIVER_VERSION_MAJOR 3
		#define DRIVER_VERSION_MINOR 1

		static void adreno_input_work(struct work_struct *work);
		static unsigned int counter_delta(struct kgsl_device *device,
		unsigned int reg, unsigned int *counter);
		@@ -2257,19 +2254,20 @@ int adreno_reset(struct kgsl_device *device, int fault)
		return ret;
		}

		static int copy_prop(void __user dst, size_t count, void src, size_t size)
		static int copy_prop(struct kgsl_device_getproperty *param,
		void *src, size_t size)
		{
		if (count != size)
		if (param->sizebytes != size)
		return -EINVAL;

		if (copy_to_user(dst, src, count))
		if (copy_to_user(param->value, src, param->sizebytes))
		return -EFAULT;

		return 0;
		}

		static int adreno_prop_device_info(struct kgsl_device *device,
		u32 type, void __user *value, size_t count)
		struct kgsl_device_getproperty *param)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		struct kgsl_devinfo devinfo = {
		@@ -2280,11 +2278,11 @@ static int adreno_prop_device_info(struct kgsl_device *device,
		.gmem_sizebytes = adreno_dev->gpucore->gmem_size,
		};

		return copy_prop(value, count, &devinfo, sizeof(devinfo));
		return copy_prop(param, &devinfo, sizeof(devinfo));
		}

		static int adreno_prop_device_shadow(struct kgsl_device *device,
		u32 type, void __user *value, size_t count)
		struct kgsl_device_getproperty *param)
		{
		struct kgsl_shadowprop shadowprop = { 0 };

		@@ -2301,11 +2299,11 @@ static int adreno_prop_device_shadow(struct kgsl_device *device,
		KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS;
		}

		return copy_prop(value, count, &shadowprop, sizeof(shadowprop));
		return copy_prop(param, &shadowprop, sizeof(shadowprop));
		}

		static int adreno_prop_device_qdss_stm(struct kgsl_device *device,
		u32 type, void __user *value, size_t count)
		struct kgsl_device_getproperty *param)
		{
		struct kgsl_qdss_stm_prop qdssprop = {0};
		struct kgsl_memdesc *qdss_desc = kgsl_mmu_get_qdss_global_entry(device);
		@@ -2315,11 +2313,11 @@ static int adreno_prop_device_qdss_stm(struct kgsl_device *device,
		qdssprop.size = qdss_desc->size;
		}

		return copy_prop(value, count, &qdssprop, sizeof(qdssprop));
		return copy_prop(param, &qdssprop, sizeof(qdssprop));
		}

		static int adreno_prop_device_qtimer(struct kgsl_device *device,
		u32 type, void __user *value, size_t count)
		struct kgsl_device_getproperty *param)
		{
		struct kgsl_qtimer_prop qtimerprop = {0};
		struct kgsl_memdesc *qtimer_desc =
		@@ -2330,33 +2328,33 @@ static int adreno_prop_device_qtimer(struct kgsl_device *device,
		qtimerprop.size = qtimer_desc->size;
		}

		return copy_prop(value, count, &qtimerprop, sizeof(qtimerprop));
		return copy_prop(param, &qtimerprop, sizeof(qtimerprop));
		}

		static int adreno_prop_s32(struct kgsl_device *device,
		u32 type, void __user *value, size_t count)
		struct kgsl_device_getproperty *param)
		{
		int val = 0;

		if (type == KGSL_PROP_MMU_ENABLE)
		if (param->type == KGSL_PROP_MMU_ENABLE)
		val = MMU_FEATURE(&device->mmu, KGSL_MMU_PAGED);
		else if (type == KGSL_PROP_INTERRUPT_WAITS)
		else if (param->type == KGSL_PROP_INTERRUPT_WAITS)
		val = 1;

		return copy_prop(value, count, &val, sizeof(val));
		return copy_prop(param, &val, sizeof(val));
		}

		static int adreno_prop_uche_gmem_addr(struct kgsl_device *device,
		u32 type, void __user *value, size_t count)
		struct kgsl_device_getproperty *param)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		u64 vaddr = adreno_dev->gpucore->gmem_base;

		return copy_prop(value, count, &vaddr, sizeof(vaddr));
		return copy_prop(param, &vaddr, sizeof(vaddr));
		}

		static int adreno_prop_ucode_version(struct kgsl_device *device,
		u32 type, void __user *value, size_t count)
		struct kgsl_device_getproperty *param)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		struct kgsl_ucode_version ucode = {
		@@ -2364,11 +2362,11 @@ static int adreno_prop_ucode_version(struct kgsl_device *device,
		.pm4 = adreno_dev->fw[ADRENO_FW_PM4].version,
		};

		return copy_prop(value, count, &ucode, sizeof(ucode));
		return copy_prop(param, &ucode, sizeof(ucode));
		}

		static int adreno_prop_gpmu_version(struct kgsl_device *device,
		u32 type, void __user *value, size_t count)
		struct kgsl_device_getproperty *param)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		struct kgsl_gpmu_version gpmu = { 0 };
		@@ -2383,64 +2381,65 @@ static int adreno_prop_gpmu_version(struct kgsl_device *device,
		gpmu.minor = adreno_dev->gpucore->gpmu_minor;
		gpmu.features = adreno_dev->gpucore->gpmu_features;

		return copy_prop(value, count, &gpmu, sizeof(gpmu));
		return copy_prop(param, &gpmu, sizeof(gpmu));
		}

		static int adreno_prop_u32(struct kgsl_device *device,
		u32 type, void __user *value, size_t count)
		struct kgsl_device_getproperty *param)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		u32 val = 0;

		if (type == KGSL_PROP_HIGHEST_BANK_BIT) {
		if (param->type == KGSL_PROP_HIGHEST_BANK_BIT) {
		if (of_property_read_u32(device->pdev->dev.of_node,
		"qcom,highest-bank-bit", &val))
		return -EINVAL;
		} else if (type == KGSL_PROP_MIN_ACCESS_LENGTH)
		} else if (param->type == KGSL_PROP_MIN_ACCESS_LENGTH)
		of_property_read_u32(device->pdev->dev.of_node,
		"qcom,min-access-length", &val);
		else if (type == KGSL_PROP_UBWC_MODE)
		else if (param->type == KGSL_PROP_UBWC_MODE)
		of_property_read_u32(device->pdev->dev.of_node,
		"qcom,ubwc-mode", &val);
		else if (type == KGSL_PROP_DEVICE_BITNESS)
		else if (param->type == KGSL_PROP_DEVICE_BITNESS)
		val = adreno_support_64bit(adreno_dev) ? 48 : 32;

		else if (type == KGSL_PROP_SPEED_BIN)
		else if (param->type == KGSL_PROP_SPEED_BIN)
		val = adreno_dev->speed_bin;

		return copy_prop(value, count, &val, sizeof(val));
		return copy_prop(param, &val, sizeof(val));
		}

		static struct {
		int (func)(struct kgsl_device device, u32 type, void __user *value,
		size_t count);
		static const struct {
		int type;
		int (func)(struct kgsl_device device,
		struct kgsl_device_getproperty *param);
		} adreno_property_funcs[] = {
		[KGSL_PROP_DEVICE_INFO] = { .func = adreno_prop_device_info },
		[KGSL_PROP_DEVICE_SHADOW] = { .func = adreno_prop_device_shadow },
		[KGSL_PROP_DEVICE_QDSS_STM] = { .func = adreno_prop_device_qdss_stm },
		[KGSL_PROP_DEVICE_QTIMER] = { .func = adreno_prop_device_qtimer },
		[KGSL_PROP_MMU_ENABLE] = { .func = adreno_prop_s32 },
		[KGSL_PROP_INTERRUPT_WAITS] = { .func = adreno_prop_s32 },
		[KGSL_PROP_UCHE_GMEM_VADDR] = { .func = adreno_prop_uche_gmem_addr },
		[KGSL_PROP_UCODE_VERSION] = { .func = adreno_prop_ucode_version },
		[KGSL_PROP_GPMU_VERSION] = { .func = adreno_prop_gpmu_version },
		[KGSL_PROP_HIGHEST_BANK_BIT] = { .func = adreno_prop_u32 },
		[KGSL_PROP_MIN_ACCESS_LENGTH] = { .func = adreno_prop_u32 },
		[KGSL_PROP_UBWC_MODE] = { .func = adreno_prop_u32 },
		[KGSL_PROP_DEVICE_BITNESS] = { .func = adreno_prop_u32 },
		[KGSL_PROP_SPEED_BIN] = { .func = adreno_prop_u32 },
		{ KGSL_PROP_DEVICE_INFO, adreno_prop_device_info },
		{ KGSL_PROP_DEVICE_SHADOW, adreno_prop_device_shadow },
		{ KGSL_PROP_DEVICE_QDSS_STM, adreno_prop_device_qdss_stm },
		{ KGSL_PROP_DEVICE_QTIMER, adreno_prop_device_qtimer },
		{ KGSL_PROP_MMU_ENABLE, adreno_prop_s32 },
		{ KGSL_PROP_INTERRUPT_WAITS, adreno_prop_s32 },
		{ KGSL_PROP_UCHE_GMEM_VADDR, adreno_prop_uche_gmem_addr },
		{ KGSL_PROP_UCODE_VERSION, adreno_prop_ucode_version },
		{ KGSL_PROP_GPMU_VERSION, adreno_prop_gpmu_version },
		{ KGSL_PROP_HIGHEST_BANK_BIT, adreno_prop_u32 },
		{ KGSL_PROP_MIN_ACCESS_LENGTH, adreno_prop_u32 },
		{ KGSL_PROP_UBWC_MODE, adreno_prop_u32 },
		{ KGSL_PROP_DEVICE_BITNESS, adreno_prop_u32 },
		{ KGSL_PROP_SPEED_BIN, adreno_prop_u32 },
		};

		static int adreno_getproperty(struct kgsl_device *device,
		unsigned int type,
		void __user *value,
		size_t sizebytes)
		struct kgsl_device_getproperty *param)
		{
		if (type >= ARRAY_SIZE(adreno_property_funcs) \|\|
		!adreno_property_funcs[type].func)
		return -EINVAL;
		int i;

		return adreno_property_funcs[type].func(device, type, value, sizebytes);
		for (i = 0; i < ARRAY_SIZE(adreno_property_funcs); i++) {
		if (param->type == adreno_property_funcs[i].type)
		return adreno_property_funcs[i].func(device, param);
		}

		return -ENODEV;
		}

		int adreno_set_constraint(struct kgsl_device *device,
		@@ -2605,6 +2604,7 @@ static int adreno_setproperty(struct kgsl_device_private *dev_priv,
		}
		break;
		default:
		status = -ENODEV;
		break;
		}

drivers/gpu/msm/adreno.h

+0 −18

Original line number	Diff line number	Diff line
		@@ -1167,26 +1167,8 @@ static inline int adreno_is_a3xx(struct adreno_device *adreno_dev)
		}

		ADRENO_TARGET(a304, ADRENO_REV_A304)
		ADRENO_TARGET(a305, ADRENO_REV_A305)
		ADRENO_TARGET(a305b, ADRENO_REV_A305B)
		ADRENO_TARGET(a305c, ADRENO_REV_A305C)
		ADRENO_TARGET(a306, ADRENO_REV_A306)
		ADRENO_TARGET(a306a, ADRENO_REV_A306A)
		ADRENO_TARGET(a310, ADRENO_REV_A310)
		ADRENO_TARGET(a320, ADRENO_REV_A320)
		ADRENO_TARGET(a330, ADRENO_REV_A330)

		static inline int adreno_is_a330v2(struct adreno_device *adreno_dev)
		{
		return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A330) &&
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) > 0));
		}

		static inline int adreno_is_a330v21(struct adreno_device *adreno_dev)
		{
		return ((ADRENO_GPUREV(adreno_dev) == ADRENO_REV_A330) &&
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) > 0xF));
		}

		static inline int adreno_is_a5xx(struct adreno_device *adreno_dev)
		{

drivers/gpu/msm/adreno_a3xx.c

+7 −208

Original line number	Diff line number	Diff line
		@@ -101,18 +101,6 @@ const unsigned int a3xx_cp_addr_regs[ADRENO_CP_ADDR_MAX] = {
		A3XX_SP_FS_OBJ_START_REG),
		};

		static unsigned int adreno_a3xx_rbbm_clock_ctl_default(struct adreno_device
		*adreno_dev)
		{
		if (adreno_is_a320(adreno_dev))
		return A320_RBBM_CLOCK_CTL_DEFAULT;
		else if (adreno_is_a330v2(adreno_dev))
		return A3XX_RBBM_CLOCK_CTL_DEFAULT;
		else if (adreno_is_a330(adreno_dev))
		return A330_RBBM_CLOCK_CTL_DEFAULT;
		return A3XX_RBBM_CLOCK_CTL_DEFAULT;
		}

		static const unsigned int _a3xx_pwron_fixup_fs_instructions[] = {
		0x00000000, 0x302CC300, 0x00000000, 0x302CC304,
		0x00000000, 0x302CC308, 0x00000000, 0x302CC30C,
		@@ -624,14 +612,9 @@ static int _a3xx_pwron_fixup(struct adreno_device *adreno_dev)

		static void a3xx_platform_setup(struct adreno_device *adreno_dev)
		{
		struct adreno_gpudev *gpudev;
		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

		if (adreno_is_a306(adreno_dev) \|\| adreno_is_a306a(adreno_dev)
		\|\| adreno_is_a304(adreno_dev)) {
		gpudev = ADRENO_GPU_DEVICE(adreno_dev);
		gpudev->vbif_xin_halt_ctrl0_mask =
		A30X_VBIF_XIN_HALT_CTRL0_MASK;
		}
		gpudev->vbif_xin_halt_ctrl0_mask = A30X_VBIF_XIN_HALT_CTRL0_MASK;

		/* Check efuse bits for various capabilties */
		a3xx_check_features(adreno_dev);
		@@ -721,19 +704,7 @@ static int a3xx_rb_start(struct adreno_device *adreno_dev)
		*/
		static void a3xx_init(struct adreno_device *adreno_dev)
		{
		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

		_a3xx_pwron_fixup(adreno_dev);

		/* Adjust snapshot section sizes according to core */
		if ((adreno_is_a330(adreno_dev) \|\| adreno_is_a305b(adreno_dev))) {
		gpudev->snapshot_data->sect_sizes->cp_pfp =
		A320_SNAPSHOT_CP_STATE_SECTION_SIZE;
		gpudev->snapshot_data->sect_sizes->roq =
		A320_SNAPSHOT_ROQ_SECTION_SIZE;
		gpudev->snapshot_data->sect_sizes->cp_merciu =
		A320_SNAPSHOT_CP_MERCIU_SECTION_SIZE;
		}
		}

		/*
		@@ -866,48 +837,6 @@ static const struct adreno_vbif_data a304_vbif[] = {
		{0, 0},
		};

		static const struct adreno_vbif_data a305_vbif[] = {
		/* Set up 16 deep read/write request queues */
		{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010 },
		{ A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010 },
		{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010 },
		{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010 },
		{ A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303 },
		{ A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010 },
		{ A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010 },
		/* Enable WR-REQ */
		{ A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000FF },
		/* Set up round robin arbitration between both AXI ports */
		{ A3XX_VBIF_ARB_CTL, 0x00000030 },
		/* Set up AOOO */
		{ A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003C },
		{ A3XX_VBIF_OUT_AXI_AOOO, 0x003C003C },
		{0, 0},
		};

		static const struct adreno_vbif_data a305b_vbif[] = {
		{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818 },
		{ A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818 },
		{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018 },
		{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018 },
		{ A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303 },
		{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },
		{0, 0},
		};

		static const struct adreno_vbif_data a305c_vbif[] = {
		{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x00101010 },
		{ A3XX_VBIF_IN_WR_LIM_CONF0, 0x00101010 },
		{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000010 },
		{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000010 },
		{ A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000101 },
		{ A3XX_VBIF_ARB_CTL, 0x00000010 },
		/* Set up AOOO */
		{ A3XX_VBIF_OUT_AXI_AOOO_EN, 0x00000007 },
		{ A3XX_VBIF_OUT_AXI_AOOO, 0x00070007 },
		{0, 0},
		};

		static const struct adreno_vbif_data a306_vbif[] = {
		{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },
		{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000A },
		@@ -922,111 +851,10 @@ static const struct adreno_vbif_data a306a_vbif[] = {
		{0, 0},
		};

		static const struct adreno_vbif_data a310_vbif[] = {
		{ A3XX_VBIF_ABIT_SORT, 0x0001000F },
		{ A3XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },
		/* Enable WR-REQ */
		{ A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000001 },
		/* Set up VBIF_ROUND_ROBIN_QOS_ARB */
		{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x3 },
		{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x18180C0C },
		{ A3XX_VBIF_IN_WR_LIM_CONF0, 0x1818000C },
		{0, 0},
		};

		static const struct adreno_vbif_data a320_vbif[] = {
		/* Set up 16 deep read/write request queues */
		{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010 },
		{ A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010 },
		{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010 },
		{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010 },
		{ A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303 },
		{ A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010 },
		{ A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010 },
		/* Enable WR-REQ */
		{ A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000FF },
		/* Set up round robin arbitration between both AXI ports */
		{ A3XX_VBIF_ARB_CTL, 0x00000030 },
		/* Set up AOOO */
		{ A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003C },
		{ A3XX_VBIF_OUT_AXI_AOOO, 0x003C003C },
		/* Enable 1K sort */
		{ A3XX_VBIF_ABIT_SORT, 0x000000FF },
		{ A3XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },
		{0, 0},
		};

		static const struct adreno_vbif_data a330_vbif[] = {
		/* Set up 16 deep read/write request queues */
		{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818 },
		{ A3XX_VBIF_IN_RD_LIM_CONF1, 0x00001818 },
		{ A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00001818 },
		{ A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00001818 },
		{ A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303 },
		{ A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818 },
		{ A3XX_VBIF_IN_WR_LIM_CONF1, 0x00001818 },
		/* Enable WR-REQ */
		{ A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003F },
		/* Set up round robin arbitration between both AXI ports */
		{ A3XX_VBIF_ARB_CTL, 0x00000030 },
		/* Set up VBIF_ROUND_ROBIN_QOS_ARB */
		{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001 },
		/* Set up AOOO */
		{ A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003F },
		{ A3XX_VBIF_OUT_AXI_AOOO, 0x003F003F },
		/* Enable 1K sort */
		{ A3XX_VBIF_ABIT_SORT, 0x0001003F },
		{ A3XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },
		/* Disable VBIF clock gating. This is to enable AXI running
		* higher frequency than GPU.
		*/
		{ A3XX_VBIF_CLKON, 1 },
		{0, 0},
		};

		/*
		* Most of the VBIF registers on 8974v2 have the correct values at power on, so
		* we won't modify those if we don't need to
		*/
		static const struct adreno_vbif_data a330v2_vbif[] = {
		/* Enable 1k sort */
		{ A3XX_VBIF_ABIT_SORT, 0x0001003F },
		{ A3XX_VBIF_ABIT_SORT_CONF, 0x000000A4 },
		/* Enable WR-REQ */
		{ A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003F },
		{ A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303 },
		/* Set up VBIF_ROUND_ROBIN_QOS_ARB */
		{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },
		{0, 0},
		};

		/*
		* Most of the VBIF registers on a330v2.1 have the correct values at power on,
		* so we won't modify those if we don't need to
		*/
		static const struct adreno_vbif_data a330v21_vbif[] = {
		/* Enable WR-REQ */
		{ A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x1 },
		/* Set up VBIF_ROUND_ROBIN_QOS_ARB */
		{ A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003 },
		{ A3XX_VBIF_IN_RD_LIM_CONF0, 0x18180c0c },
		{0, 0},
		};

		static const struct adreno_vbif_platform a3xx_vbif_platforms[] = {
		{ adreno_is_a304, a304_vbif },
		{ adreno_is_a305, a305_vbif },
		{ adreno_is_a305c, a305c_vbif },
		{ adreno_is_a306, a306_vbif },
		{ adreno_is_a306a, a306a_vbif },
		{ adreno_is_a310, a310_vbif },
		{ adreno_is_a320, a320_vbif },
		/* A330v2.1 needs to be ahead of A330v2 so the right device matches */
		{ adreno_is_a330v21, a330v21_vbif},
		/* A330v2 needs to be ahead of A330 so the right device matches */
		{ adreno_is_a330v2, a330v2_vbif },
		{ adreno_is_a330, a330_vbif },
		{ adreno_is_a305b, a305b_vbif },
		};

		/*
		@@ -1260,13 +1088,7 @@ static void a3xx_perfcounter_init(struct adreno_device *adreno_dev)
		{
		struct adreno_perfcounters *counters = ADRENO_PERFCOUNTERS(adreno_dev);

		/* SP[3] counter is broken on a330 so disable it if a330 device */
		if (adreno_is_a330(adreno_dev))
		a3xx_perfcounters_sp[3].countable = KGSL_PERFCOUNTER_BROKEN;

		if (counters &&
		(adreno_is_a306(adreno_dev) \|\| adreno_is_a304(adreno_dev) \|\|
		adreno_is_a306a(adreno_dev))) {
		if (counters) {
		counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF].regs =
		a3xx_perfcounters_vbif2;
		counters->groups[KGSL_PERFCOUNTER_GROUP_VBIF_PWR].regs =
		@@ -1335,7 +1157,6 @@ static void a3xx_protect_init(struct adreno_device *adreno_dev)
		static void a3xx_start(struct adreno_device *adreno_dev)
		{
		struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
		struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);

		adreno_vbif_start(adreno_dev, a3xx_vbif_platforms,
		ARRAY_SIZE(a3xx_vbif_platforms));
		@@ -1364,12 +1185,6 @@ static void a3xx_start(struct adreno_device *adreno_dev)
		* Turn on hang detection - this spews a lot of useful information
		* into the RBBM registers on a hang
		*/
		if (adreno_is_a330v2(adreno_dev)) {
		set_bit(ADRENO_DEVICE_HANG_INTR, &adreno_dev->priv);
		gpudev->irq->mask \|= (1 << A3XX_INT_MISC_HANG_DETECT);
		kgsl_regwrite(device, A3XX_RBBM_INTERFACE_HANG_INT_CTL,
		(1 << 31) \| 0xFFFF);
		} else
		kgsl_regwrite(device, A3XX_RBBM_INTERFACE_HANG_INT_CTL,
		(1 << 16) \| 0xFFF);

		@@ -1380,18 +1195,7 @@ static void a3xx_start(struct adreno_device *adreno_dev)
		kgsl_regwrite(device, A3XX_UCHE_CACHE_WAYS_VFD, 0x07);

		/* Enable Clock gating */
		kgsl_regwrite(device, A3XX_RBBM_CLOCK_CTL,
		adreno_a3xx_rbbm_clock_ctl_default(adreno_dev));

		if (adreno_is_a330v2(adreno_dev))
		kgsl_regwrite(device, A3XX_RBBM_GPR0_CTL,
		A330v2_RBBM_GPR0_CTL_DEFAULT);
		else if (adreno_is_a330(adreno_dev))
		kgsl_regwrite(device, A3XX_RBBM_GPR0_CTL,
		A330_RBBM_GPR0_CTL_DEFAULT);
		else if (adreno_is_a310(adreno_dev))
		kgsl_regwrite(device, A3XX_RBBM_GPR0_CTL,
		A310_RBBM_GPR0_CTL_DEFAULT);
		kgsl_regwrite(device, A3XX_RBBM_CLOCK_CTL, A3XX_RBBM_CLOCK_CTL_DEFAULT);

		/* Turn on protection */
		a3xx_protect_init(adreno_dev);
		@@ -1402,11 +1206,6 @@ static void a3xx_start(struct adreno_device *adreno_dev)
		kgsl_regwrite(device, A3XX_CP_DEBUG, A3XX_CP_DEBUG_DEFAULT);

		/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
		if (adreno_is_a305b(adreno_dev) \|\|
		adreno_is_a310(adreno_dev) \|\|
		adreno_is_a330(adreno_dev))
		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x003E2008);
		else
		kgsl_regwrite(device, A3XX_CP_QUEUE_THRESHOLDS, 0x000E0602);

		}

drivers/gpu/msm/adreno_a3xx_snapshot.c

+24 −58

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
		* Copyright (c) 2012-2017,2019, The Linux Foundation. All rights reserved.
		*/

		#include <linux/io.h>
		@@ -143,27 +143,14 @@ static size_t a3xx_snapshot_shader_memory(struct kgsl_device *device,
		static size_t a3xx_snapshot_debugbus_block(struct kgsl_device *device,
		u8 buf, size_t remain, void priv)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

		struct kgsl_snapshot_debugbus *header
		= (struct kgsl_snapshot_debugbus *)buf;
		struct adreno_debugbus_block *block = priv;
		int i;
		unsigned int data = (unsigned int )(buf + sizeof(*header));
		unsigned int dwords;
		size_t size;

		/*
		* For A305 and A320 all debug bus regions are the same size (0x40). For
		* A330, they can be different sizes - most are still 0x40, but some
		* like CP are larger
		*/

		dwords = (adreno_is_a330(adreno_dev) \|\|
		adreno_is_a305b(adreno_dev)) ?
		block->dwords : 0x40;

		size = (dwords * sizeof(unsigned int)) + sizeof(*header);
		size = (0x40 * sizeof(unsigned int)) + sizeof(*header);

		if (remain < size) {
		SNAPSHOT_ERR_NOMEM(device, "DEBUGBUS");
		@@ -171,9 +158,9 @@ static size_t a3xx_snapshot_debugbus_block(struct kgsl_device *device,
		}

		header->id = block->block_id;
		header->count = dwords;
		header->count = 0x40;

		for (i = 0; i < dwords; i++)
		for (i = 0; i < 0x40; i++)
		_rbbm_debug_bus_read(device, block->block_id, i, &data[i]);

		return size;
		@@ -225,7 +212,7 @@ static void a3xx_snapshot_debugbus(struct kgsl_device *device,
		static void _snapshot_hlsq_regs(struct kgsl_device *device,
		struct kgsl_snapshot *snapshot)
		{
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
		unsigned int next_pif = 0;

		/*
		* Trying to read HLSQ registers when the HLSQ block is busy
		@@ -236,22 +223,6 @@ static void _snapshot_hlsq_regs(struct kgsl_device *device,
		* dump the registers, otherwise dump the HLSQ registers.
		*/

		if (adreno_is_a330(adreno_dev)) {
		/*
		* stall_ctxt_full status bit: RBBM_BLOCK_ID_HLSQ index 49 [27]
		*
		* if (!stall_context_full)
		* then dump HLSQ registers
		*/
		unsigned int stall_context_full = 0;

		_rbbm_debug_bus_read(device, RBBM_BLOCK_ID_HLSQ, 49,
		&stall_context_full);
		stall_context_full &= 0x08000000;

		if (stall_context_full)
		return;
		} else {
		/*
		* tpif status bits: RBBM_BLOCK_ID_HLSQ index 4 [4:0]
		* spif status bits: RBBM_BLOCK_ID_HLSQ index 7 [5:0]
		@@ -259,7 +230,6 @@ static void _snapshot_hlsq_regs(struct kgsl_device *device,
		* if ((tpif == 0, 1, 28) && (spif == 0, 1, 10))
		* then dump HLSQ registers
		*/
		unsigned int next_pif = 0;

		/* check tpif */
		_rbbm_debug_bus_read(device, RBBM_BLOCK_ID_HLSQ, 4, &next_pif);
		@@ -272,7 +242,6 @@ static void _snapshot_hlsq_regs(struct kgsl_device *device,
		next_pif &= 0x3f;
		if (next_pif != 0 && next_pif != 1 && next_pif != 10)
		return;
		}

		SNAPSHOT_REGISTERS(device, snapshot, a3xx_hlsq_registers);
		}
		@@ -301,9 +270,6 @@ void a3xx_snapshot(struct adreno_device *adreno_dev,

		_snapshot_hlsq_regs(device, snapshot);

		if (adreno_is_a330(adreno_dev) \|\| adreno_is_a305b(adreno_dev))
		SNAPSHOT_REGISTERS(device, snapshot, a330_registers);

		kgsl_snapshot_indexed_registers(device, snapshot,
		A3XX_CP_STATE_DEBUG_INDEX, A3XX_CP_STATE_DEBUG_DATA,
		0x0, snap_data->sect_sizes->cp_pfp);

drivers/gpu/msm/adreno_compat.c

+8 −11

Original line number	Diff line number	Diff line
		@@ -12,19 +12,17 @@
		#include "adreno_compat.h"

		int adreno_getproperty_compat(struct kgsl_device *device,
		unsigned int type,
		void __user *value,
		size_t sizebytes)
		struct kgsl_device_getproperty *param)
		{
		int status = -EINVAL;
		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

		switch (type) {
		switch (param->type) {
		case KGSL_PROP_DEVICE_INFO:
		{
		struct kgsl_devinfo_compat devinfo;

		if (sizebytes != sizeof(devinfo)) {
		if (param->sizebytes != sizeof(devinfo)) {
		status = -EINVAL;
		break;
		}
		@@ -39,8 +37,8 @@ int adreno_getproperty_compat(struct kgsl_device *device,
		devinfo.gmem_sizebytes =
		adreno_dev->gpucore->gmem_size;

		if (copy_to_user(value, &devinfo, sizeof(devinfo)) !=
		0) {
		if (copy_to_user(param->value, &devinfo,
		sizeof(devinfo))) {
		status = -EFAULT;
		break;
		}
		@@ -51,7 +49,7 @@ int adreno_getproperty_compat(struct kgsl_device *device,
		{
		struct kgsl_shadowprop_compat shadowprop;

		if (sizebytes != sizeof(shadowprop)) {
		if (param->sizebytes != sizeof(shadowprop)) {
		status = -EINVAL;
		break;
		}
		@@ -75,7 +73,7 @@ int adreno_getproperty_compat(struct kgsl_device *device,
		shadowprop.flags = KGSL_FLAGS_INITIALIZED \|
		KGSL_FLAGS_PER_CONTEXT_TIMESTAMPS;
		}
		if (copy_to_user(value, &shadowprop,
		if (copy_to_user(param->value, &shadowprop,
		sizeof(shadowprop))) {
		status = -EFAULT;
		break;
		@@ -84,8 +82,7 @@ int adreno_getproperty_compat(struct kgsl_device *device,
		}
		break;
		default:
		status = device->ftbl->getproperty(device, type, value,
		sizebytes);
		status = device->ftbl->getproperty(device, param);
		}

		return status;