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Commit da612d88 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: add more Haswell PCI IDs



Also properly indent the HB IDs.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5ab3633d
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+34 −5
Original line number Diff line number Diff line
@@ -242,13 +242,42 @@
#define PCI_DEVICE_ID_INTEL_HASWELL_HB			0x0400 /* Desktop */
#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG		0x0402
#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG		0x0412
#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG	0x0422
#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB		0x0404 /* Mobile */
#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG		0x0406
#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG		0x0416
#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG	0x0426
#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB		0x0408 /* Server */
#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG		0x040a
#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG		0x041a
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV		0x0c16 /* SDV */
#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG	0x042a
#define PCI_DEVICE_ID_INTEL_HASWELL_E_HB		0x0c04
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG	0x0C02
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG	0x0C12
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG	0x0C22
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG	0x0C06
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG	0x0C16
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG	0x0C26
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG	0x0C0A
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG	0x0C1A
#define PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG	0x0C2A
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG	0x0A02
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG	0x0A12
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG	0x0A22
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG	0x0A06
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG	0x0A16
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG	0x0A26
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG	0x0A0A
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG	0x0A1A
#define PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG	0x0A2A
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG	0x0D12
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG	0x0D22
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG	0x0D32
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG	0x0D16
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG	0x0D26
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG	0x0D36
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG	0x0D1A
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG	0x0D2A
#define PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG	0x0D3A

#endif
+59 −1
Original line number Diff line number Diff line
@@ -1502,15 +1502,73 @@ static const struct intel_gtt_driver_description {
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV,
	{ PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG,
	    "Haswell", &sandybridge_gtt_driver },
	{ 0, NULL, NULL }
};
+30 −1
Original line number Diff line number Diff line
@@ -346,11 +346,40 @@ static const struct pci_device_id pciidlist[] = { /* aka */
	INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
	INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
	INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
	INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
	INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
	INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
	INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
	INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
	INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
	INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */
	INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
	INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
	INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
	INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
	INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
	INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
	INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
	INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
	INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
	INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
	INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
	INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
	INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
	INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
	INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
	INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
	INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
	INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
	INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
	INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
	INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
	INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
	INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
	INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
	INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
	INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
	INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
	INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
	INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
	INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
	INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),