Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit da4ee13c authored by Vince Hsu's avatar Vince Hsu Committed by Ben Skeggs
Browse files

drm/nouveau/fifo/gk104: fix engine status register offset 



The offset should be 8 on Kepler and later.

Signed-off-by: default avatarVince Hsu <vinceh@nvidia.com>
Reviewed-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 864d55f4

drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c

+1 −1
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo) 


	spin_lock_irqsave(&fifo->base.lock, flags);

	for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) {

		u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04));

		u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));

		u32 busy = (stat & 0x80000000);

		u32 next = (stat & 0x07ff0000) >> 16;

		u32 chsw = (stat & 0x00008000);