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Commit da3bc50a authored by Ram Prakash Gupta's avatar Ram Prakash Gupta Committed by Gerrit - the friendly Code Review server
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mmc: host: sdhci-msm: Toggle FIFO write clk after MCLK ungated 



During GCC level clock gating of MCLK, the async FIFO
gets into some hang condition, such that for the next
transfer after MCLK ungating, first bit of CMD response
doesn't get written in to the FIFO. This cause the CPSM
to hang eventually leading to SW timeout.

To fix the issue, toggle the FIFO write clock after
MCLK ungated to get the FIFO pointers and flags to
valid states.

Change-Id: I29faefbcb814fcc36fb8afcf7ec2cb51c553b5e6
Signed-off-by: default avatarRam Prakash Gupta <rampraka@codeaurora.org>
parent db92782e

drivers/mmc/host/sdhci-msm.c

+29 −0
Original line number Diff line number Diff line
@@ -167,6 +167,8 @@ 
#define MAX_DRV_TYPES_SUPPORTED_HS200	4

#define MSM_AUTOSUSPEND_DELAY_MS 100



#define RCLK_TOGGLE 0x2



struct sdhci_msm_offset {

	u32 CORE_MCI_DATA_CNT;

	u32 CORE_MCI_STATUS;
@@ -3723,6 +3725,33 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) 
					| CORE_HC_SELECT_IN_EN), host->ioaddr +

					msm_host_offset->CORE_VENDOR_SPEC);

		}

		/*

		 * After MCLK ugating, toggle the FIFO write clock to get

		 * the FIFO pointers and flags to valid state.

		 */

		if (msm_host->tuning_done ||

				(card && mmc_card_strobe(card) &&

				msm_host->enhanced_strobe)) {

			/*

			 * set HC_REG_DLL_CONFIG_3[1] to select MCLK as

			 * DLL input clock

			 */

			writel_relaxed(((readl_relaxed(host->ioaddr +

				msm_host_offset->CORE_DDR_CONFIG))

				| RCLK_TOGGLE), host->ioaddr +

				msm_host_offset->CORE_DDR_CONFIG);

			/* ensure above write as toggling same bit quickly */

			wmb();

			udelay(2);

			/*

			 * clear HC_REG_DLL_CONFIG_3[1] to select RCLK as

			 * DLL input clock

			 */

			writel_relaxed(((readl_relaxed(host->ioaddr +

				msm_host_offset->CORE_DDR_CONFIG))

				& ~RCLK_TOGGLE), host->ioaddr +

				msm_host_offset->CORE_DDR_CONFIG);

		}

		if (!host->mmc->ios.old_rate && !msm_host->use_cdclp533) {

			/*

			 * Poll on DLL_LOCK and DDR_DLL_LOCK bits in