Commit d9d8e6b3 authored Dec 11, 2014 by Sonika Jindal Committed by Daniel Vetter Dec 15, 2014

drm/i915/skl: Correcting the flushing of pipe



We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Satheeshakrishna <M&lt;satheeshakrishna.m@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

parent 27401d12

drivers/gpu/drm/i915/intel_pm.c

+1 −2

Original line number	Diff line number	Diff line
		@@ -3004,10 +3004,9 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
		skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
		skl_wm_flush_pipe(dev_priv, pipe, 2);
		intel_wait_for_vblank(dev, pipe);
		}

		reallocated[pipe] = true;
		}
		}

		/*
		* Third pass: flush the pipes that got more space allocated.