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Commit d9bed144 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: dts: omap4-droid4: Add LCD 



The LCD panel on droid 4 is a command mode LCD. The binding follows
the standard omapdrm binding and the changes needed for omapdrm command
mode panels are posted separately.

Cc: devicetree@vger.kernel.org
Cc: Marcel Partap <mpartap@gmx.net>
Cc: Michael Scott <michael.scott@linaro.org>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-By: default avatarSebastian Reichel <sre@kernel.org>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 50cdcc0b

arch/arm/boot/dts/omap4-droid4-xt894.dts

+60 −0
Original line number Diff line number Diff line
@@ -17,6 +17,11 @@ 
		stdout-path = &uart3;

	};



	aliases {

		display0 = &lcd0;

		display1 = &hdmi0;

	};



	/*

	 * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,

	 * then 1023 - 1024 seems to contain mbm. For SRAM, see the notes
@@ -66,6 +71,17 @@ 
		regulator-always-on;

	};



	/* LCD regulator from sw5 source */

	lcd_regulator: regulator-lcd {

		compatible = "regulator-fixed";

		regulator-name = "lcd";

		regulator-min-microvolt = <5050000>;

		regulator-max-microvolt = <5050000>;

		gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;	/* gpio96 */

		enable-active-high;

		vin-supply = <&sw5>;

	};



	/* This is probably coming straight from the battery.. */

	wl12xx_vmmc: regulator-wl12xx {

		compatible = "regulator-fixed";
@@ -111,6 +127,50 @@ 
	};

};



&dsi1 {

	status = "okay";

	vdd-supply = <&vcsi>;



	port {

		dsi1_out_ep: endpoint {

			remote-endpoint = <&lcd0_in>;

			lanes = <0 1 2 3 4 5>;

		};

	};



	lcd0: display {

		compatible = "panel-dsi-cm";

		label = "lcd0";

		vddi-supply = <&lcd_regulator>;

		reset-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;	/* gpio101 */



		panel-timing {

			clock-frequency = <0>;		/* Calculated by dsi */



			hback-porch = <2>;

			hactive = <540>;

			hfront-porch = <0>;

			hsync-len = <2>;



			vback-porch = <1>;

			vactive = <960>;

			vfront-porch = <0>;

			vsync-len = <1>;



			hsync-active = <0>;

			vsync-active = <0>;

			de-active = <1>;

			pixelclk-active = <1>;

		};



		port {

			lcd0_in: endpoint {

				remote-endpoint = <&dsi1_out_ep>;

			};

		};

	};

};



/* L3_2 interconnect is unused, SRAM, GPMC and L3_ICLK2 disabled */

&gpmc {

	status = "disabled";